kernel/linux.git/Documentation/devicetree/bindings/interrupt-controller, branch v7.2-rc1

Merge tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2026-06-17T18:54:57+00:00

Pull devicetree updates from Rob Herring: "DT core: - Add support for handling multiple cells in "iommu-map" entries - Support only 1 entry in /reserved-memory "reg" entries. Support for more than 1 entry has been broken - Fix a UAF on alloc_reserved_mem_array() failure - Make "ibm,phandle" handling logic specific to PPC - Use memcpy() instead of strcpy() for known length strings - Ensure __of_find_n_match_cpu_property() handles malformed "reg" entries - Add various checks that expected strings are strings before accessing them - Drop redundant memset() when unflattening DT DT bindings: - Add a DTS style checker. Currently hooked up to dt_binding_check to check examples - Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar bindings to DT schema - Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas - Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc, qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys - Consolidate "sram" property definitions - Fix constraints on "nvmem" properties which only contain phandles and no arg cells - Another pass of fixing "phandle-array" constraints - Add Gira vendor prefix" * tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits) dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema dt-bindings: vendor-prefixes: add Gira dt-bindings: embedded-controller: Add Qualcomm reference device EC description dt-bindings: pwm: add IPQ6018 binding dt-bindings: hwmon: Add Apple System Management Controller hwmon schema docs: dt: writing-schema: Clarify what is required in a schema of: Respect #{iommu,msi}-cells in maps of: Factor arguments passed to of_map_id() into a struct of: Add convenience wrappers for of_map_id() of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry of: reserved_mem: handle NULL name in of_reserved_mem_lookup() dt-bindings: cache: l2c2x0: Add missing power-domains dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries drivers/of/overlay: Use memcpy() to copy known length strings dt-bindings: add self-test fixtures for style checker dt-bindings: wire style checker into dt_binding_check scripts/jobserver-exec: propagate child exit status dt-bindings: add DTS style checker ...

Merge tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2026-06-17T18:16:56+00:00

Pull SoC devicetree updates from Arnd Bergmann: "There are fewer devicetree updates this time that the last few ones, with five SoC types getting added: - Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using four Cortex-A55 and one Cortex-A78 core, which is a significant upgrade from older generations - ZTE zx297520v3 is an older low-end wireless SoC using a single Cortex-A53 core, which so far can only run 32-bit kernels. This brings back the ZX family of chips that was removed in 2021 after support for the original zx296702 and zx296718 chips was never completed. - Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N (R8A77965) automotive SoC. - Apple t8122 (M3) is the 2023 generation of their laptop SoCs, which has now been reverse-engineered to the point of having initial kernel support for five laptop models. - ASPEED AST27xx is their first baseboard managment controller using a 64-bit core, the Cortex-A35, following earlier generations using ARMv5/v6/v7 CPUs. These all come with one or more initial boards, and in total there are 39 new boards getting added across SoC families, including: - Two NAS boxes using the old Cortina Systems Gemini SoC based on an ARMv4 FA526 CPU core - 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A SoCs from Variscite, Toradex and SolidRun, plus a number of overlays for combinations with additional boards - One new carrier board and SoM using TI K3 AM62x, in addition to new overlays for older SoMs - Two new boards using Spacemit K3 (no relation with TI) RISC-V SoCs. - Three phones from Google, Nothing and Motorola, all using Qualcomm Snapdragon SoCs - AST26xx BMC support for two server boards While there is still a significant number of patches improving hardware support for the existing boards across vendors (NXP, Qualcomm, Renesas, Rockchips, Mediatek, ...), a much smaller number of cleanups and warning fixes have made it in this time" * tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (665 commits) arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme arm64: dts: bst: enable eMMC controller in C1200 dt-bindings: display/lvds-codec: add ti,sn65lvds93 arm64: dts: allwinner: a523: Add missing GPIO interrupt arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap arm64: dts: aspeed: Add initial AST27xx SoC device tree arm64: Kconfig: Add ASPEED SoC family Kconfig support dt-bindings: arm: aspeed: Add AST2700 board compatible arm64: dts: allwinner: a523: add gpadc node arm64: dts: allwinner: Add EL2 virtual timer interrupt ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays arm64: dts: imx93-var-som-symphony: enable ADC arm64: dts: imx93-var-som-symphony: enable TPM3 PWM arm64: dts: imx93-var-som-symphony: keep RGB_SEL low arm64: dts: imx93-var-som-symphony: enable UART7 arm64: dts: imx93-var-som-symphony: add TPM support arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling ...

dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string

2026-06-16T13:53:12+00:00

Register qcom,maili-pdc as a supported compatible string for the Qualcomm PDC interrupt controller binding. Signed-off-by: Yijie Yang Link: https://patch.msgid.link/20260615-maili-pdc-v1-1-add21e8eec3e@oss.qualcomm.com Signed-off-by: Rob Herring (Arm)

dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema

2026-06-15T18:55:54+00:00

Convert TI irq-crossbar binding from text format to DT schema. As part of conversion following changes are made: - Add '#interrupt-cells' as a required property which was missing in text binding - As irq-crossbar is interrupt-controller. Move binding from bindings/arm/omap to bindings/interrupt-controller Signed-off-by: Bhargav Joshi Link: https://patch.msgid.link/20260612-crossbar-v3-1-266747bc2e86@gmail.com Signed-off-by: Rob Herring (Arm)

dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example

2026-06-10T20:15:59+00:00

According to Figure 5.1 ("Unified memory map"), the safety register block is 64 KiB large, just like the non-safety register block. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/364ff570c8a1845fab24bd89557f06c9e406f8de.1781105007.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm)

dt-bindings: soc: sophgo: add sg2000 plic and clint documentation

2026-06-02T08:23:57+00:00

Document the compatible strings for the sg2000 interrupt controller and timer. Signed-off-by: Joshua Milas Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260530173347.33533-4-josh.milas@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang

dt-bindings: interrupt-controller: Document PDC for Qualcomm Nord SoC

2026-05-13T12:53:13+00:00

Document Power Domain Controller on Qualcomm Nord SoC. Signed-off-by: Shawn Guo Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260504080703.825328-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm)

dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping

2026-05-11T13:29:30+00:00

In MIPS VEIC mode (Vectored External Interrupt Controller), the hardware stops directly dispatching CPU interrupts such as IPIs or CPU performance counters, and instead it communicates them to the external interrupt controller (the hardware described here) which prioritizes, renumbers, and integrates them with its own hardware interrupt pins. Interrupts from the external controller are then dispatched through a different method via a dispatch table. In effect, the external controller subsumes the CPU controller and becomes the root. 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136 Since there are interrupts which ought to be controlled by the CPU controller driver - particularly the IPI interrupts - we create a reverse mapping where those interrupts may be sent back to the CPU intc when they are received. This maintains the fiction that there is still a hierarchy, and keeps the DT the same no matter whether the processor is in VEIC mode or not. The econet,cpu-interrupt-map is optional and if omitted, it's assumed that no interrupts need to be mapped. Signed-off-by: Caleb James DeLisle Signed-off-by: Thomas Gleixner Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr

dt-bindings: interrupt-controller: Add support for Amlogic A9 SoCs

2026-05-11T13:11:29+00:00

Update dt-binding document for GPIO interrupt controller of Amlogic A9 SoCs. Signed-off-by: Xianwei Zhao Signed-off-by: Thomas Gleixner Acked-by: Conor Dooley Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-2-9dc5f3e022e0@amlogic.com

dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 for jhb100

2026-04-30T10:53:04+00:00

The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Acked-by: Conor Dooley Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com