kernel/linux.git/Documentation/devicetree/bindings/interconnect, branch v7.1-rc5

Merge branch 'icc-msm8974' into icc-next

2026-03-27T10:12:36+00:00

Commit d6edc31f3a68 ("clk: qcom: smd-rpm: Separate out interconnect bus clocks") moved control over several RPM resources from the clk-smd-rpm driver to the icc-rpm.c interconnect helpers. Most of the platforms were fixed before that commit or shortly after. However the MSM8974 was left as a foster child in broken state. Fix the loose ends and reenable interconnects on that platform. * icc-msm8974 dt-bindings: interconnect: qcom,msm8974: drop bus clocks dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-common interconnect: qcom: drop unused is_on flag interconnect: qcom: icc-rpm: allow overwriting get_bw callback interconnect: qcom: define OCMEM bus resource interconnect: qcom: let platforms declare their bugginess interconnect: qcom: msm8974: switch to the main icc-rpm driver interconnect: qcom: msm8974: expand DEFINE_QNODE macros Link: https://msgid.link/20260324-msm8974-icc-v2-0-527280043ad8@oss.qualcomm.com Tested-by: Alexandre Messier Tested-by: Luca Weiss # fairphone-fp2 Signed-off-by: Georgi Djakov

dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-common

2026-03-26T18:09:13+00:00

Use qcom,rpm-common schema to declare interconnects property instead describing it again. In future this will allow the platform to switch to the two-cell interconnects, adding the tag to the specification. Signed-off-by: Dmitry Baryshkov Link: https://msgid.link/20260324-msm8974-icc-v2-2-527280043ad8@oss.qualcomm.com Signed-off-by: Georgi Djakov

dt-bindings: interconnect: qcom,msm8974: drop bus clocks

2026-03-26T18:08:56+00:00

Remove the wrong internal RPM bus clock representation that we've been carrying for years. They are an internal part of the interconnect fabric. They are not exported by any device and are not supposed to be used. Signed-off-by: Dmitry Baryshkov Link: https://msgid.link/20260324-msm8974-icc-v2-1-527280043ad8@oss.qualcomm.com Signed-off-by: Georgi Djakov

Merge branch 'icc-qcs615' into icc-next

2026-03-17T10:57:00+00:00

This series enables QoS configuration for QNOC type device which can be found on QCS615 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-qcs615 dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS interconnect: qcom: qcs615: enable QoS configuration Link: https://msgid.link/20260311103548.1823044-1-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov

dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

2026-03-17T10:42:42+00:00

Aggre1-noc interconnect node on QCS615 has QoS registers located inside a block whose interface is clock-gated. Accessing these registers requires the corresponding clock(s) to be enabled. Update the bindings to include the 'clocks' property. Ensure that only aggre1-noc interconnect node uses this property by explicitly forbidding it for all other interconnect nodes. Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Link: https://msgid.link/20260311103548.1823044-2-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov

Merge branch 'icc-qcs8300' into icc-next

2026-03-06T12:39:37+00:00

This series enables QoS configuration for QNOC type device which can be found on QCS8300 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-qcs8300 dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS interconnect: qcom: qcs8300: enable QoS configuration Link: https://msgid.link/20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov

Merge branch 'icc-mahua' into icc-next

2026-03-06T12:38:48+00:00

Mahua is a derivative of the Glymur SoC and shares a significant portion of its interconnect topology with Glymur. As such, this series extends the existing Glymur interconnect driver to support Mahua, reusing common definitions where possible and adding SoC-specific configurations where necessary. * icc-mahua dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC interconnect: qcom: glymur: Add Mahua SoC support Link: https://msgid.link/20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov

Merge branch 'icc-eliza' into icc-next

2026-03-06T12:37:35+00:00

Add interconnect support for the Qualcomm Eliza SoC. * icc-eliza dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC interconnect: qcom: Add Eliza interconnect provider driver dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible Signed-off-by: Georgi Djakov

dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC

2026-03-06T12:32:11+00:00

Document the RPMh Network-On-Chip Interconnect of the Eliza platform. Signed-off-by: Odelu Kukatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://msgid.link/20260224-eliza-interconnect-v4-1-ad75855d5018@oss.qualcomm.com Signed-off-by: Georgi Djakov

dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible

2026-03-06T12:32:10+00:00

Eliza, similarly to SM8650, uses EPSS hardware for L3 scaling. Document it. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Link: https://msgid.link/20260302-eliza-bindings-interconnect-epss-l3-v2-1-05b1848b98cc@oss.qualcomm.com Signed-off-by: Georgi Djakov