Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v5.19 2022-07-06T16:27:05+00:00 2022-07-06T16:27:05+00:00 Samuel Holland samuel@sholland.org 2022-07-02T03:19:02+00:00 urn:sha1:607a48c78e6b427b0b684d24e61c19e846ad65d6 The conditional block for variants with a second clock should have set minItems, not maxItems, which was already 2. Since clock-names requires two items, this typo should not have caused any problems. Fixes: edd14218bd66 ("dt-bindings: dmaengine: Convert Allwinner A31 and A64 DMA to a schema") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220702031903.21703-1-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-05-29T18:38:27+00:00 Linus Torvalds torvalds@linux-foundation.org 2022-05-29T18:38:27+00:00 urn:sha1:b00ed48bb0a7c295facf9036135a573a5cdbe7de Pull dmaengine updates from Vinod Koul: "Nothing special, this includes a couple of new device support and new driver support and bunch of driver updates. New support: - Tegra gpcdma driver support - Qualcomm SM8350, Sm8450 and SC7280 device support - Renesas RZN1 dma and platform support Updates: - stm32 device pause/resume support and updates - DMA memset ops Documentation and usage clarification - deprecate '#dma-channels' & '#dma-requests' bindings - driver updates for stm32, ptdma idsx etc" * tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (87 commits) dmaengine: idxd: make idxd_wq_enable() return 0 if wq is already enabled dmaengine: sun6i: Add support for the D1 variant dmaengine: sun6i: Add support for 34-bit physical addresses dmaengine: sun6i: Do not use virt_to_phys dt-bindings: dma: sun50i-a64: Add compatible for D1 dmaengine: tegra: Remove unused switch case dmaengine: tegra: Fix uninitialized variable usage dmaengine: stm32-dma: add device_pause/device_resume support dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done() dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg dmaengine: stm32-dmamux: avoid reset of dmamux if used by coprocessor dmaengine: qcom: gpi: Add support for sc7280 dt-bindings: dma: pl330: Add power-domains dmaengine: stm32-mdma: use dev_dbg on non-busy channel spurious it dmaengine: stm32-mdma: fix chan initialization in stm32_mdma_irq_handler() dmaengine: stm32-mdma: remove GISR1 register dmaengine: ti: deprecate '#dma-channels' dmaengine: mmp: deprecate '#dma-channels' dmaengine: pxa: deprecate '#dma-channels' and '#dma-requests' ... 2022-05-26T17:28:12+00:00 Linus Torvalds torvalds@linux-foundation.org 2022-05-26T17:28:12+00:00 urn:sha1:ae862183285cbb2ef9032770d98ffa9becffe9d5 Pull ARM DT updates from Arnd Bergmann: "There are 40 branches this time, adding a lot of new hardware support, and cleanups. Krzysztof Kozlowski continues his treewide cleanups. There are a number of new SoCs, all of them as part of existing families, and typically added along with a reference board: - Renesas RZ/G2UL (R9A07G043) is the single-core version of the RZ/G2L general-purpose MPU. - Renesas RZ/V2M (R9A09G011) is a smart camera SoC - Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76 cores and deep learning accerlation. - Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7 and dual Wifi-6. - Corstone1000 is a generic platform from Arm that is used for designing custom SoCs, the support for now is for the Fixed Virtual Platform emulation for it. - Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used in upcoming Chromebooks. - NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first MMU-less SoC to be added in a while New machines based on already supported SoCs this time are mainly for 32-bit platforms and include: - Two wireless routers based on Broadcom bcm4708 - 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly for the industrial embedded market, and on NXP LS1021A based IOT board. - Two ethernet switches based on Microchip LAN966 - Eight Qualcomm Snapdragon based machines, including a smartwatch, a Chromebook board and some phones - Another phone based on the old ST-Ericsson Ux500 platform - Seven STM32MP1 based boards - Four single-board computers based on Rockchip RK3566/RK3568" * tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (791 commits) ARM: dts: kswitch-d10: enable networking ARM: dts: lan966x: add switch node ARM: dts: lan966x: add serdes node ARM: dts: lan966x: add reset switch reset node ARM: dts: lan966x: add MIIM nodes ARM: dts: lan966x: add hwmon node ARM: dts: lan966x: add basic Kontron KSwitch D10 support ARM: dts: lan966x: add flexcom I2C nodes ARM: dts: lan966x: add flexcom SPI nodes ARM: dts: lan966x: add all flexcom usart nodes ARM: dts: lan966x: add missing uart DMA channel ARM: dts: lan966x: add sgpio node ARM: dts: lan966x: swap dma channels for crypto node ARM: dts: lan966x: rename pinctrl nodes ARM: dts: at91: sama7g5: remove interrupt-parent from gic node ARM: dts: at91: use generic node name for dataflash ARM: dts: turris-omnia: Add atsha204a node arm64: dts: mt8192: Follow binding order for SCP registers arm64: dts: mediatek: add mtk-snfi for mt7622 arm64: dts: mediatek: mt8195-demo: enable uart1 ... 2022-05-25T21:56:06+00:00 Linus Torvalds torvalds@linux-foundation.org 2022-05-25T21:56:06+00:00 urn:sha1:86c87bea6b42100c67418af690919c44de6ede6e Pull devicetree updates from Rob Herring: "Bindings: - Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm, qcom,i2c-qup, qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new props), qcom,smp2p, TI timer, Mediatek gnss, Mediatek topckgen, Mediatek apmixedsys, Mediatek infracfg, fsl,ls-extirq, fsl,layerscape-dcfg, QCom PMIC SPMI, rda,8810pl-timer, Xilinx zynqmp_ipi, uniphier-pcie, and Ilitek touchscreen controllers - Convert various Arm Ltd peripheral IP bindings to schemas - New bindings for Menlo board CPLD, DH electronics board CPLD, Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751 GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and Microchip/SMSC LAN95xx USB Ethernet controllers - Add vendor prefix for Enclustra - Add various compatible string additions - Various example fixes and cleanups - Remove unused hisilicon,hi6220-reset binding - Treewide fix properties missing type definition - Drop some empty and unreferenced .txt bindings - Documentation improvements for writing schemas DT driver core: - Drop static IRQ resources for DT platform devices as IRQ setup is dynamic and drivers have all been converted to use platform_get_irq() and friends - Rework memory allocations and frees for overlays - Continue overlay notifier callbacks on successful calls and add unittests - Handle 'interrupts-extended' in early DT IRQ setup - Fix of_property_read_string() errors to match documentation - Ignore disabled nodes in FDT API calls" * tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (86 commits) of/irq: fix typo in comment dt-bindings: Fix properties without any type Revert "dt-bindings: mailbox: qcom-ipcc: add missing properties into example" dt-bindings: input: touchscreen: ilitek_ts_i2c: Absorb ili2xxx bindings dt-bindings: timer: samsung,exynos4210-mct: define strict clock order dt-bindings: timer: samsung,exynos4210-mct: drop unneeded minItems dt-bindings: timer: cdns,ttc: drop unneeded minItems dt-bindings: mailbox: zynqmp_ipi: convert to yaml dt-bindings: usb: ci-hdrc-usb2: fix node node for ethernet controller dt-bindings: net: add schema for Microchip/SMSC LAN95xx USB Ethernet controllers dt-bindings: net: add schema for ASIX USB Ethernet controllers of/fdt: Ignore disabled memory nodes dt-bindings: arm: fix typos in compatible dt-bindings: mfd: Add bindings child nodes for the Mediatek MT6360 dt-bindings: display: convert Arm Komeda to DT schema dt-bindings: display: convert Arm Mali-DP to DT schema dt-bindings: display: convert Arm HDLCD to DT schema dt-bindings: display: convert PL110/PL111 to DT schema dt-bindings: arm: convert vexpress-config to DT schema dt-bindings: arm: convert vexpress-sysregs to DT schema ... 2022-05-19T18:13:41+00:00 Samuel Holland samuel@sholland.org 2022-04-24T17:27:55+00:00 urn:sha1:59e477763d092923f567051e1bbfbb4e04d0dfbf D1 has a DMA controller similar to the one in other Allwinner SoCs. Add its compatible, and include it in the list of variants with a separate MBUS clock gate. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220424172759.33383-2-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-05-19T17:51:28+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2022-04-27T06:40:48+00:00 urn:sha1:6c3c2066d6dc317fd05893d4ce07b2f3633e3e2a The pl330 DMA controller on Exynos SoC (e.g. dma-controller@3880000 in Exynos5420) belongs to power domain, so allow such property. Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220427064048.86635-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-05-19T17:23:46+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2022-05-03T06:54:04+00:00 urn:sha1:bd1eca7b2c66c53873a0eab84f9f301aca41f33a The generic properties, used in most of the drivers and defined in generic dma-common DT bindings, are 'dma-channels' and 'dma-requests'. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220503065407.52188-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-05-19T17:04:51+00:00 Miquel Raynal miquel.raynal@bootlin.com 2022-04-27T09:56:47+00:00 urn:sha1:7ac92262e1fb574ee4da2944b83e412aa0ae2ab4 Just like for the NAND controller that is also on this SoC, let's provide a SoC generic and a more specific couple of compatibles for the DMA controller. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220427095653.91804-4-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-05-19T17:04:51+00:00 Miquel Raynal miquel.raynal@bootlin.com 2022-04-27T09:56:45+00:00 urn:sha1:6cd4154a266584ca3908305ce64e14a5f0f3e81f The Renesas RZN1 DMA IP is based on a DW core, with eg. an additional dmamux register located in the system control area which can take up to 32 requests (16 per DMA controller). Each DMA channel can be wired to two different peripherals. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220427095653.91804-2-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2022-05-16T13:04:35+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2022-05-03T06:51:45+00:00 urn:sha1:54326f37ec134c138dad4ae33bea048b0b186dd3 The generic property, used in most of the drivers and defined in generic dma-common DT bindings, is 'dma-channels'. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220503065147.51728-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>