kernel/linux.git/Documentation/devicetree/bindings/cpufreq, branch master

dt-bindings: cpufreq: qcom-hw: document Eliza cpufreq hardware

2026-03-03T04:10:16+00:00

Document the cpufreq hardware on the Eliza SoC. Signed-off-by: Abel Vesa Signed-off-by: Viresh Kumar

dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware

2026-01-27T05:51:22+00:00

Document the CPUFREQ Hardware on the Milos SoC. Acked-by: Rob Herring (Arm) Acked-by: Viresh Kumar Signed-off-by: Luca Weiss Signed-off-by: Viresh Kumar

Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-10-02T00:32:51+00:00

Pull SoC driver updates from Arnd Bergmann: "Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0" * tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits) soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu() soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Change GPIO driver to a proper platform driver tee: fix register_shm_helper() pmdomain: apple: Add "apple,t8103-pmgr-pwrstate" dt-bindings: spmi: Add Apple A11 and T2 compatible serial: qcom-geni: Load UART qup Firmware from linux side spi: geni-qcom: Load spi qup Firmware from linux side i2c: qcom-geni: Load i2c qup Firmware from linux side soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem soc: qcom: geni-se: Cleanup register defines and update copyright dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Documentation: tee: Add Qualcomm TEE driver tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl tee: qcom: add primordial object tee: add Qualcomm TEE driver tee: increase TEE_MAX_ARG_SIZE to 4096 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF tee: add close_context to TEE driver operation ...

dt-bindings: cpufreq: apple,cluster-cpufreq: Add t6020 compatible

2025-09-14T19:49:19+00:00

The CPU frequency control on M2 Pro/Max/Ultra SoCs is compatible to the M2 (T8112) one. So add this with the per-SoC compatible to the bindings. Reviewed-by: Neal Gompa Acked-by: Rob Herring (Arm) Signed-off-by: Janne Grunau

dt-bindings: Remove outdated cpufreq-dt.txt

2025-08-28T05:43:39+00:00

The information present in this file is outdated and doesn't serve any purpose with the current design of the driver. Remove the outdated file. Signed-off-by: Frank Li [ Viresh: Rewrite commit log ] Signed-off-by: Viresh Kumar

dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible

2025-08-12T04:46:21+00:00

Document compatible for cpufreq hardware on Qualcomm QCS615 platform. Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski Signed-off-by: Viresh Kumar

dt-bindings: cpufreq: Add mediatek,mt8196-cpufreq-hw binding

2025-08-11T06:49:01+00:00

The MediaTek MT8196 SoC has new cpufreq hardware, with added memory register ranges to control Dynamic-Voltage-Frequency-Scaling. The DVFS hardware is controlled through a set of registers referred to as "FDVFS". They set the target frequency the DVFS hardware should aim for for each performance domain. Instead of working around the old binding and its already established meanings for the reg items, add a new binding. The FDVFS register memory region is at the beginning, which allows us to easily expand this binding for future SoCs which may have more than 3 performance domains. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Viresh Kumar

dt-bindings: cpufreq: Drop redundant Mediatek binding

2025-04-22T14:40:07+00:00

The Mediatek CPUFreq binding document just describes properties from the CPU node which the driver uses. This is redundant as all the properties are described in the arm/cpus.yaml schema. Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sudeep Holla Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-17-63d7dc9ddd0a@kernel.org

dt-bindings: cpufreq: cpufreq-qcom-hw: Narrow properties on SDX75, SA8775p and SM8650

2025-03-17T06:05:24+00:00

Add SDX75 and SA8775p compatibles to respective if:then: blocks to narrow their properties and add a new section for SM8650 with four 'reg' and 'interrupts' (top-level already allows four). SA8755p DTS comes without interrupts, but only because they might not be available for OS under given firmware. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Viresh Kumar

dt-bindings: cpufreq: cpufreq-qcom-hw: Drop redundant minItems:1

2025-03-17T06:05:24+00:00

List cannot have 0 items, so 'minItems: 1' in each if:then: is redundant. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Viresh Kumar