kernel/linux.git/Documentation/devicetree/bindings/cache, branch v6.6.132

dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example

2023-10-04T13:33:11+00:00

The unit address in the example does not match the reg property. Correct the unit address to match reality. Fixes: 3e7bf4685e42786d ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller") Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/7b93655219a6ad696dd3faa9f36fde6b094694a9.1696330005.git.geert+renesas@glider.be Signed-off-by: Rob Herring

dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller

2023-09-01T16:08:58+00:00

Add DT binding documentation for L2 cache controller found on RZ/Five SoC. The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt

dt-bindings: cache: qcom,llcc: Fix SM8550 description

2023-05-25T04:11:19+00:00

SM8550 (LLCCv4.1) has 4 register regions, this was not described between its addition and the restructurization that happened in the commit referenced in the fixes tag. Fix it. Fixes: 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks") Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-kailua-llcc-v1-1-d57bd860c43e@linaro.org

Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2023-04-27T16:23:57+00:00

Pull devicetree updates from Rob Herring: "Bindings: - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba TC358764 display bridge, Parade PS8622 display bridge, and Xilinx FPGA bindings to DT schema format - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt controller - Add MediaTek MT8365 UART and SYSIRQ bindings - Add Arm Cortex-A78C and X1C core compatibles - Add vendor prefix for Novatek - Remove bindings for stih415, sti416, stid127 platforms - Drop uneeded quotes in schema files. This is preparation for yamllint checking quoting for us. - Add missing (unevaluated|additional)Properties constraints on child node schemas - Clean-up schema comments formatting - Fix I2C and SPI node bus names in schema examples - Clean-up some display compatibles schema syntax - Fix incorrect references to lvds.yaml - Gather all cache controller bindings in a common directory DT core: - Convert unittest to new void .remove platform device hook - kerneldoc fixes for DT address of_pci_range_to_resource/ of_address_to_resource functions" * tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits) dt-bindings: rng: Drop unneeded quotes dt-bindings: arm/soc: mediatek: Drop unneeded quotes dt-bindings: soc: qcom: Drop unneeded quotes dt-bindings: i2c: samsung: Fix 'deprecated' value dt-bindings: display: Fix lvds.yaml references dt-bindings: display: simplify compatibles syntax dt-bindings: display: mediatek: simplify compatibles syntax dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references dt-bindings: timer: Drop unneeded quotes dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p dt-bindings: reset: remove stih415/stih416 reset dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127 dt-bindings: irqchip: sti: remove stih415/stih416 and stid127 dt-bindings: iommu: Convert QCOM IOMMU to YAML dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas of: address: Reshuffle to remove forward declarations of: address: Fix documented return value of of_pci_range_to_resource() of: address: Document return value of of_address_to_resource() ...

dt-bindings: move cache controller bindings to a cache directory

2023-04-04T17:12:13+00:00

There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring