kernel/linux.git/Documentation/devicetree/bindings/cache, branch v6.19.11

Merge tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-12-06T01:47:59+00:00

Pull more SoC driver updates from Arnd Bergmann: "These updates came a little late, or were based on a later 6.18-rc tag than the others: - A new driver for cache management on cxl devices with memory shared in a coherent cluster. This is part of the drivers/cache/ tree, but unlike the other drivers that back the dma-mapping interfaces, this one is needed only during CPU hotplug. - A shared branch for reset controllers using swnode infrastructure - Added support for new SoC variants in the Amlogic soc_device identification - Minor updates in Freescale, Microchip, Samsung, and Apple SoC drivers" * tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits) soc: samsung: exynos-pmu: fix device leak on regmap lookup soc: samsung: exynos-pmu: Fix structure initialization soc: fsl: qbman: use kmalloc_array() instead of kmalloc() soc: fsl: qbman: add WQ_PERCPU to alloc_workqueue users MAINTAINERS: Update email address for Christophe Leroy MAINTAINERS: refer to intended file in STANDALONE CACHE CONTROLLER DRIVERS cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent cache: Make top level Kconfig menu a boolean dependent on RISCV MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header arm64: Select GENERIC_CPU_CACHE_MAINTENANCE lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION soc: amlogic: meson-gx-socinfo: add new SoCs id dt-bindings: arm: amlogic: meson-gx-ao-secure: support more SoCs memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() dt-bindings: cache: sifive,ccache0: add a pic64gx compatible MAINTAINERS: rename Microchip RISC-V entry MAINTAINERS: add new soc drivers to Microchip RISC-V entry soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC ...

dt-bindings: cache: sifive,ccache0: add a pic64gx compatible

2025-11-17T23:44:12+00:00

The pic64gx use the same IP than mpfs, therefore add compatibility with mpfs as fallback. Signed-off-by: Pierre-Henry Moussay Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley

dt-bindings: cache: qcom,llcc: Document the Kaanapali LLCC

2025-10-22T22:21:30+00:00

Document the Last Level Cache Controller on Kaanapali platform. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250924-knp-llcc-v1-1-ae6a016e5138@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

2025-08-28T16:34:45+00:00

The QiLai implementation of this cache controller uses a cache-sets of 2048, and mandates it in an if/else block - but the definition of the property only permits 1024. Add 2048 as an option, and deny its use outside of the QiLai. Fixes: 51b081cdb9237 ("dt-bindings: cache: add QiLai compatible to ax45mp") Reviewed-by: Ben Zong-You Xie Signed-off-by: Conor Dooley

Merge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

2025-05-21T21:14:37+00:00

RISC-V cache drivers for v6.16 SiFive: Add support for the Eswin EIC7700 SoC, which needs to make sure of the non-standard cache-ops provided by the ccache driver. Bindings: Conversions for two Marvell bindings to yaml, and additions of two soc-specific compatibles to the axm45mp bindings. Signed-off-by: Conor Dooley * tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: cache: add QiLai compatible to ax45mp dt-bindings: cache: Convert marvell,tauros2-cache to DT schema dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema dt-bindings: cache: add specific RZ/Five compatible to ax45mp cache: sifive_ccache: Add ESWIN EIC7700 support dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Link: https://lore.kernel.org/r/20250516-liability-facility-667fc14a2a85@spud Signed-off-by: Arnd Bergmann

dt-bindings: cache: add QiLai compatible to ax45mp

2025-05-14T15:53:02+00:00

Add a new compatible string for ax45mp-cache on QiLai SoC. Also, add allOf constraints to enforce specific cache-sets and cache-size values for qilai-ax45mp-cache. Signed-off-by: Ben Zong-You Xie Signed-off-by: Conor Dooley

dt-bindings: cache: Convert marvell,tauros2-cache to DT schema

2025-05-13T14:43:02+00:00

Convert the Marvell Tauros2 Cache binding to DT schema. Signed-off-by: Rob Herring (Arm) Reviewed-by: Andrew Lunn Signed-off-by: Conor Dooley

dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema

2025-05-13T14:42:27+00:00

Convert the Marvell Feroceon/Kirkwood Cache binding to DT schema format. Use "marvell,kirkwood-cache" for the filename instead as that's only compatible used in a .dts upstream. Signed-off-by: Rob Herring (Arm) Reviewed-by: Andrew Lunn Signed-off-by: Conor Dooley

dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block

2025-05-12T21:26:21+00:00

Add documentation for the SM8750 LLCC. Signed-off-by: Melody Olvera Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-1-d78dca6282a5@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: cache: add specific RZ/Five compatible to ax45mp

2025-05-12T15:53:29+00:00

When the binding was originally written, it was assumed that all ax45mp-caches had the same properties etc. This has turned out to be incorrect, as the QiLai SoC has a different number of cache-sets. Add a specific compatible for the RZ/Five for property enforcement and in case there turns out to be additional differences between these implementations of the cache controller. Acked-by: Ben Zong-You Xie Reviewed-by: Geert Uytterhoeven Signed-off-by: Conor Dooley