kernel/linux.git/Documentation/devicetree/bindings/cache, branch v6.18.21

dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

2025-08-28T16:34:45+00:00

The QiLai implementation of this cache controller uses a cache-sets of 2048, and mandates it in an if/else block - but the definition of the property only permits 1024. Add 2048 as an option, and deny its use outside of the QiLai. Fixes: 51b081cdb9237 ("dt-bindings: cache: add QiLai compatible to ax45mp") Reviewed-by: Ben Zong-You Xie Signed-off-by: Conor Dooley

Merge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

2025-05-21T21:14:37+00:00

RISC-V cache drivers for v6.16 SiFive: Add support for the Eswin EIC7700 SoC, which needs to make sure of the non-standard cache-ops provided by the ccache driver. Bindings: Conversions for two Marvell bindings to yaml, and additions of two soc-specific compatibles to the axm45mp bindings. Signed-off-by: Conor Dooley * tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: cache: add QiLai compatible to ax45mp dt-bindings: cache: Convert marvell,tauros2-cache to DT schema dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema dt-bindings: cache: add specific RZ/Five compatible to ax45mp cache: sifive_ccache: Add ESWIN EIC7700 support dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Link: https://lore.kernel.org/r/20250516-liability-facility-667fc14a2a85@spud Signed-off-by: Arnd Bergmann

dt-bindings: cache: add QiLai compatible to ax45mp

2025-05-14T15:53:02+00:00

Add a new compatible string for ax45mp-cache on QiLai SoC. Also, add allOf constraints to enforce specific cache-sets and cache-size values for qilai-ax45mp-cache. Signed-off-by: Ben Zong-You Xie Signed-off-by: Conor Dooley

dt-bindings: cache: Convert marvell,tauros2-cache to DT schema

2025-05-13T14:43:02+00:00

Convert the Marvell Tauros2 Cache binding to DT schema. Signed-off-by: Rob Herring (Arm) Reviewed-by: Andrew Lunn Signed-off-by: Conor Dooley

dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema

2025-05-13T14:42:27+00:00

Convert the Marvell Feroceon/Kirkwood Cache binding to DT schema format. Use "marvell,kirkwood-cache" for the filename instead as that's only compatible used in a .dts upstream. Signed-off-by: Rob Herring (Arm) Reviewed-by: Andrew Lunn Signed-off-by: Conor Dooley

dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block

2025-05-12T21:26:21+00:00

Add documentation for the SM8750 LLCC. Signed-off-by: Melody Olvera Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-1-d78dca6282a5@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: cache: add specific RZ/Five compatible to ax45mp

2025-05-12T15:53:29+00:00

When the binding was originally written, it was assumed that all ax45mp-caches had the same properties etc. This has turned out to be incorrect, as the QiLai SoC has a different number of cache-sets. Add a specific compatible for the RZ/Five for property enforcement and in case there turns out to be additional differences between these implementations of the cache controller. Acked-by: Ben Zong-You Xie Reviewed-by: Geert Uytterhoeven Signed-off-by: Conor Dooley

dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility

2025-04-07T15:53:46+00:00

This cache controller is also used on the ESWIN EIC7700 SoC. However, it have 256KB private L2 Cache and shared L3 Cache of 4MB. So add dedicated compatible string for it. Signed-off-by: Pritesh Patel Reviewed-by: Samuel Holland Signed-off-by: Pinkesh Vaghela Signed-off-by: Conor Dooley

dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible

2025-01-08T02:16:21+00:00

Document the Last Level Cache Controller on IPQ5424. The 'broadcast' register space is present only in chipsets that have multiple instances of LLCC IP. Since IPQ5424 has only one instance, both the LLCC and LLCC_BROADCAST points to the same register space. Hence, allow only '1' reg & reg-names entry for IPQ5424. Reviewed-by: Rob Herring (Arm) Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20241121051935.1055222-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson

Merge tag 'soc-drivers-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2024-11-20T23:40:54+00:00

Pull SoC driver updates from Arnd Bergmann: "Nothing particular important in the SoC driver updates, just the usual improvements to for drivers/soc and a couple of subsystems that don't fit anywhere else: - The largest set of updates is for Qualcomm SoC drivers, extending the set of supported features for additional SoCs in the QSEECOM, LLCC and socinfo drivers.a - The ti_sci firmware driver gains support for power managment - The drivers/reset subsystem sees a rework of the microchip sparx5 and amlogic reset drivers to support additional chips, plus a few minor updates on other platforms - The SCMI firmware interface driver gains support for two protocol extensions, allowing more flexible use of the shared memory area and new DT binding properties for configurability. - Mediatek SoC drivers gain support for power managment on the MT8188 SoC and a new driver for DVFS. - The AMD/Xilinx ZynqMP SoC drivers gain support for system reboot and a few bugfixes - The Hisilicon Kunpeng HCCS driver gains support for configuring lanes through sysfs Finally, there are cleanups and minor fixes for drivers/{soc, bus, memory}, including changing back the .remove_new callback to .remove, as well as a few other updates for freescale (powerpc) soc drivers, NXP i.MX soc drivers, cznic turris platform driver, memory controller drviers, TI OMAP SoC drivers, and Tegra firmware drivers" * tag 'soc-drivers-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (116 commits) soc: fsl: cpm1: qmc: Set the ret error code on platform_get_irq() failure soc: fsl: rcpm: fix missing of_node_put() in copy_ippdexpcr1_setting() soc: fsl: cpm1: tsa: switch to for_each_available_child_of_node_scoped() platform: cznic: turris-omnia-mcu: Rename variable holding GPIO line names platform: cznic: turris-omnia-mcu: Document the driver private data structure firmware: turris-mox-rwtm: Document the driver private data structure bus: Switch back to struct platform_driver::remove() soc: qcom: ice: Remove the device_link field in qcom_ice drm/msm/adreno: Setup SMMU aparture for per-process page table firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID firmware: arm_scpi: Check the DVFS OPP count returned by the firmware soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404 soc: qcom: llcc: Flip the manual slice configuration condition dt-bindings: firmware: qcom,scm: Document sm8750 SCM firmware: qcom: uefisecapp: Allow X1E Devkit devices misc: lan966x_pci: Fix dtc warn 'Missing interrupt-parent' misc: lan966x_pci: Fix dtc warns 'missing or empty reg/ranges property' soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC ...