kernel/linux.git/Documentation/devicetree/bindings/cache, branch master

Merge tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

2026-04-02T21:19:52+00:00

Qualcomm driver updates for v7.1 Add ECS LIVA QC710, Glymur CRD, Mahua CRD, Purwa IoT EVK, and Asus Vivobook to the QSEECOM allow-list, to enable UEFI variable access through uefisecapp. Register the Gunyah watchdog device if the SCM driver finds itself running under Gunyah. Clean up some locking using guards. Handle possible cases where AOSS cooling state is given a non-boolean state. Replace LLCC per-slice activation bitmap with reference counting. Also add SDM670 support. Improve probe deferral handling in the OCMEM driver. Add Milos, QCS615, Eliza, Glymur, and Mahua support to the pd-mapper. Add support for SoCCP-based pmic-glink, as found in Glymur and Kaanapali. Add common QMI service ids to the main qmi headerfile, to avoid spreading these constants in various drivers. Add support for version 2 of SMP2P and implement the irqchip state reading support. Add CQ7790, SA8650P, SM7450, SM7450P, and IPQ5210 SoC and the PM7550BA PMIC identifiers to the socinfo driver. Add Eliza and Mahua support to the UBWC driver, introduce helpers for drivers to read out min_acc length and other programmable values, and disable bank swizzling for Glymur. Simplify the logic related to allocation of NV download request in the WCNSS control driver. * tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (51 commits) soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset dt-bindings: firmware: qcom,scm: Document ipq9650 SCM soc: qcom: ubwc: Add support for Mahua soc: qcom: pd-mapper: Add support for Glymur and Mahua soc: qcom: ubwc: Add configuration Eliza SoC soc: qcom: ubwc: Remove redundant x1e80100_data dt-bindings: firmware: qcom,scm: document Eliza SCM Firmware Interface soc: qcom: ocmem: return -EPROBE_DEFER is ocmem is not available soc: qcom: ocmem: register reasons for probe deferrals soc: qcom: ocmem: make the core clock optional soc: qcom: ubwc: disable bank swizzling for Glymur platform ... Signed-off-by: Arnd Bergmann

dt-bindings: cache: qcom,llcc: Add SDM670 compatible

2026-03-16T01:25:24+00:00

Document the Last Level Cache Controller on SDM670. Signed-off-by: Richard Acayan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260210021957.13357-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson

dt-bindings: cache: bt1-l2-ctl: Remove unused bindings

2026-02-26T07:28:16+00:00

As stated in [1] the Baikal platforms are not supported and the respective driver code has just been removed. Remove unused bindings. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Acked-by: Conor Dooley Signed-off-by: Andy Shevchenko Link: https://patch.msgid.link/20260225173930.3819351-3-andriy.shevchenko@linux.intel.com Signed-off-by: Krzysztof Kozlowski

dt-bindings: cache: qcom,llcc: Remove duplicate llcc7_base for Glymur

2026-01-05T14:57:12+00:00

Drop redundant llcc7_base entry from Glymur LLCC reg-items Fixes: bd0b8028ce5f ("dt-bindings: cache: qcom,llcc: Document Glymur LLCC block") Signed-off-by: Pankaj Patil Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260105130050.1062903-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: cache: qcom,llcc: Document Glymur LLCC block

2025-12-16T23:23:18+00:00

Document the Last Level Cache Controller on Glymur SoC Glymur LLCC has 12 base register regions and an additional AND, OR broadcast region, total 14 register regions Increase maxItems for reg and reg-names to allow 14 entries for Glymur Reviewed-by: Krzysztof Kozlowski Signed-off-by: Pankaj Patil Link: https://lore.kernel.org/r/20251211-glymur_llcc_enablement-v3-1-43457b354b0d@oss.qualcomm.com Signed-off-by: Bjorn Andersson

Merge tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-12-06T01:47:59+00:00

Pull more SoC driver updates from Arnd Bergmann: "These updates came a little late, or were based on a later 6.18-rc tag than the others: - A new driver for cache management on cxl devices with memory shared in a coherent cluster. This is part of the drivers/cache/ tree, but unlike the other drivers that back the dma-mapping interfaces, this one is needed only during CPU hotplug. - A shared branch for reset controllers using swnode infrastructure - Added support for new SoC variants in the Amlogic soc_device identification - Minor updates in Freescale, Microchip, Samsung, and Apple SoC drivers" * tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits) soc: samsung: exynos-pmu: fix device leak on regmap lookup soc: samsung: exynos-pmu: Fix structure initialization soc: fsl: qbman: use kmalloc_array() instead of kmalloc() soc: fsl: qbman: add WQ_PERCPU to alloc_workqueue users MAINTAINERS: Update email address for Christophe Leroy MAINTAINERS: refer to intended file in STANDALONE CACHE CONTROLLER DRIVERS cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent cache: Make top level Kconfig menu a boolean dependent on RISCV MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header arm64: Select GENERIC_CPU_CACHE_MAINTENANCE lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION soc: amlogic: meson-gx-socinfo: add new SoCs id dt-bindings: arm: amlogic: meson-gx-ao-secure: support more SoCs memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() dt-bindings: cache: sifive,ccache0: add a pic64gx compatible MAINTAINERS: rename Microchip RISC-V entry MAINTAINERS: add new soc drivers to Microchip RISC-V entry soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC ...

dt-bindings: cache: sifive,ccache0: add a pic64gx compatible

2025-11-17T23:44:12+00:00

The pic64gx use the same IP than mpfs, therefore add compatibility with mpfs as fallback. Signed-off-by: Pierre-Henry Moussay Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley

dt-bindings: cache: qcom,llcc: Document the Kaanapali LLCC

2025-10-22T22:21:30+00:00

Document the Last Level Cache Controller on Kaanapali platform. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250924-knp-llcc-v1-1-ae6a016e5138@oss.qualcomm.com Signed-off-by: Bjorn Andersson

dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

2025-08-28T16:34:45+00:00

The QiLai implementation of this cache controller uses a cache-sets of 2048, and mandates it in an if/else block - but the definition of the property only permits 1024. Add 2048 as an option, and deny its use outside of the QiLai. Fixes: 51b081cdb9237 ("dt-bindings: cache: add QiLai compatible to ax45mp") Reviewed-by: Ben Zong-You Xie Signed-off-by: Conor Dooley

Merge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

2025-05-21T21:14:37+00:00

RISC-V cache drivers for v6.16 SiFive: Add support for the Eswin EIC7700 SoC, which needs to make sure of the non-standard cache-ops provided by the ccache driver. Bindings: Conversions for two Marvell bindings to yaml, and additions of two soc-specific compatibles to the axm45mp bindings. Signed-off-by: Conor Dooley * tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: cache: add QiLai compatible to ax45mp dt-bindings: cache: Convert marvell,tauros2-cache to DT schema dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema dt-bindings: cache: add specific RZ/Five compatible to ax45mp cache: sifive_ccache: Add ESWIN EIC7700 support dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Link: https://lore.kernel.org/r/20250516-liability-facility-667fc14a2a85@spud Signed-off-by: Arnd Bergmann