<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git, branch v6.4.10</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.4.10</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.4.10'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-08-11T10:14:29+00:00</updated>
<entry>
<title>Linux 6.4.10</title>
<updated>2023-08-11T10:14:29+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2023-08-11T10:14:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b269b0268d4121d033721775d6e0c1114acfe50b'/>
<id>urn:sha1:b269b0268d4121d033721775d6e0c1114acfe50b</id>
<content type='text'>
Link: https://lore.kernel.org/r/20230809103642.720851262@linuxfoundation.org
Tested-by: Ronald Warsow &lt;rwarsow@gmx.de&gt;
Tested-by: Joel Fernandes (Google) &lt;joel@joelfernandes.org&gt;
Tested-by: Justin M. Forbes &lt;jforbes@fedoraproject.org&gt;
Tested-by: SeongJae Park &lt;sj@kernel.org&gt;
Tested-by: Salvatore Bonaccorso &lt;carnil@debian.org&gt;
Tested-by: Ron Economos &lt;re@w6rz.net&gt;
Tested-by: Florian Fainelli &lt;florian.fainelli@broadcom.com&gt;
Tested-by: Bagas Sanjaya &lt;bagasdotme@gmail.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Tested-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Tested-by: Miguel Ojeda &lt;ojeda@kernel.org&gt; # Rust
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>x86/CPU/AMD: Do not leak quotient data after a division by 0</title>
<updated>2023-08-11T10:14:29+00:00</updated>
<author>
<name>Borislav Petkov (AMD)</name>
<email>bp@alien8.de</email>
</author>
<published>2023-08-04T22:06:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c9c0b889e2d33d49b06bb716b95a192ed3449173'/>
<id>urn:sha1:c9c0b889e2d33d49b06bb716b95a192ed3449173</id>
<content type='text'>
commit 77245f1c3c6495521f6a3af082696ee2f8ce3921 upstream.

Under certain circumstances, an integer division by 0 which faults, can
leave stale quotient data from a previous division operation on Zen1
microarchitectures.

Do a dummy division 0/1 before returning from the #DE exception handler
in order to avoid any leaks of potentially sensitive data.

Signed-off-by: Borislav Petkov (AMD) &lt;bp@alien8.de&gt;
Cc: &lt;stable@kernel.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the CS</title>
<updated>2023-08-11T10:14:28+00:00</updated>
<author>
<name>Andi Shyti</name>
<email>andi.shyti@linux.intel.com</email>
</author>
<published>2023-07-25T00:19:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=493c80a4f20b741fded847b51ff73ccd7887cc74'/>
<id>urn:sha1:493c80a4f20b741fded847b51ff73ccd7887cc74</id>
<content type='text'>
[ Upstream commit 824df77ab2107d8d4740b834b276681a41ae1ac8 ]

Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).

For the copy engine add MI_FLUSH_DW_CCS (bit 16) in the command
streamer.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet")
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Cc: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.8+
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-6-andi.shyti@linux.intel.com
(cherry picked from commit b70df82b428774875c7c56d3808102165891547c)
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/i915/gt: Support aux invalidation on all engines</title>
<updated>2023-08-11T10:14:28+00:00</updated>
<author>
<name>Andi Shyti</name>
<email>andi.shyti@linux.intel.com</email>
</author>
<published>2023-07-25T00:19:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=43f5167d2cdcbd78665456ddea5b1c4f1af1c496'/>
<id>urn:sha1:43f5167d2cdcbd78665456ddea5b1c4f1af1c496</id>
<content type='text'>
[ Upstream commit 6a35f22d222528e1b157c6978c9424d2f8cbe0a1 ]

Perform some refactoring with the purpose of keeping in one
single place all the operations around the aux table
invalidation.

With this refactoring add more engines where the invalidation
should be performed.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.8+
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-8-andi.shyti@linux.intel.com
(cherry picked from commit 76ff7789d6e63d1a10b3b58f5c70b2e640c7a880)
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/i915/gt: Poll aux invalidation register bit on invalidation</title>
<updated>2023-08-11T10:14:28+00:00</updated>
<author>
<name>Jonathan Cavitt</name>
<email>jonathan.cavitt@intel.com</email>
</author>
<published>2023-07-25T00:19:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e66e37671c18e8f2965f38cac99753e1ab0772f7'/>
<id>urn:sha1:e66e37671c18e8f2965f38cac99753e1ab0772f7</id>
<content type='text'>
[ Upstream commit 0fde2f23516a00fd90dfb980b66b4665fcbfa659 ]

For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.8+
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-7-andi.shyti@linux.intel.com
(cherry picked from commit d459c86f00aa98028d155a012c65dc42f7c37e76)
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/i915/gt: Rename flags with bit_group_X according to the datasheet</title>
<updated>2023-08-11T10:14:28+00:00</updated>
<author>
<name>Andi Shyti</name>
<email>andi.shyti@linux.intel.com</email>
</author>
<published>2023-07-25T00:19:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=10be2cb87f0a19bc93ea483ba48cfcc1f8e0f5bc'/>
<id>urn:sha1:10be2cb87f0a19bc93ea483ba48cfcc1f8e0f5bc</id>
<content type='text'>
[ Upstream commit 592b228f12e15867a63e3a6eeeb54c5c12662a62 ]

In preparation of the next patch align with the datasheet (BSPEC
47112) with the naming of the pipe control set of flag values.
The variable "flags" in gen12_emit_flush_rcs() is applied as a
set of flags called Bit Group 1.

Define also the Bit Group 0 as bit_group_0 where currently only
PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set.

Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.8+
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-5-andi.shyti@linux.intel.com
(cherry picked from commit f2dcd21d5a22e13f2fbfe7ab65149038b93cf2ff)
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/i915/gt: Add workaround 14016712196</title>
<updated>2023-08-11T10:14:28+00:00</updated>
<author>
<name>Tejas Upadhyay</name>
<email>tejas.upadhyay@intel.com</email>
</author>
<published>2023-06-01T11:09:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=73400908a97b305d21e993ad76d2a23a44302b1e'/>
<id>urn:sha1:73400908a97b305d21e993ad76d2a23a44302b1e</id>
<content type='text'>
[ Upstream commit d922b80b1010cd6164fa7d3c197b4fbf94b47beb ]

For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.

Bspec: 72197

V5:
  - Remove ret variable - Andi
V4:
  - Update commit message, avoid returing cs - Andi/Matt
V3:
  - Wrap dummy pipe control stuff in API - Andi
V2:
  - Fix  kernel test robot warnings

Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
Signed-off-by: Tejas Upadhyay &lt;tejas.upadhyay@intel.com&gt;
Reviewed-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230601110959.1715927-1-tejas.upadhyay@intel.com
Stable-dep-of: 592b228f12e1 ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/i915/gt: Ensure memory quiesced before invalidation</title>
<updated>2023-08-11T10:14:28+00:00</updated>
<author>
<name>Jonathan Cavitt</name>
<email>jonathan.cavitt@intel.com</email>
</author>
<published>2023-07-25T00:19:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=17b66e10b134879deb9cbe8d6c0ac40d59f647a1'/>
<id>urn:sha1:17b66e10b134879deb9cbe8d6c0ac40d59f647a1</id>
<content type='text'>
[ Upstream commit 78a6ccd65fa3a7cc697810db079cc4b84dff03d5 ]

All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Requires: a2a4aa0eef3b ("drm/i915: Add the gen12_needs_ccs_aux_inv helper")
Signed-off-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.8+
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-4-andi.shyti@linux.intel.com
(cherry picked from commit ad8ebf12217e451cd19804b1c3e97ad56491c74a)
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add the gen12_needs_ccs_aux_inv helper</title>
<updated>2023-08-11T10:14:27+00:00</updated>
<author>
<name>Andi Shyti</name>
<email>andi.shyti@linux.intel.com</email>
</author>
<published>2023-07-25T00:19:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c0660d36ecd8d5751a94a796b716a6e0b113cb22'/>
<id>urn:sha1:c0660d36ecd8d5751a94a796b716a6e0b113cb22</id>
<content type='text'>
[ Upstream commit b2f59e9026038a5bbcbc0019fa58f963138211ee ]

We always assumed that a device might either have AUX or FLAT
CCS, but this is an approximation that is not always true, e.g.
PVC represents an exception.

Set the basis for future finer selection by implementing a
boolean gen12_needs_ccs_aux_inv() function that tells whether aux
invalidation is needed or not.

Currently PVC is the only exception to the above mentioned rule.

Requires: 059ae7ae2a1c ("drm/i915/gt: Cleanup aux invalidation registers")
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Cc: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v5.8+
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-3-andi.shyti@linux.intel.com
(cherry picked from commit c827655b87ad201ebe36f2e28d16b5491c8f7801)
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node</title>
<updated>2023-08-11T10:14:27+00:00</updated>
<author>
<name>Xu Yang</name>
<email>xu.yang_2@nxp.com</email>
</author>
<published>2023-07-17T02:28:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7f87080d2e9744f67da17121363729c21cba4e53'/>
<id>urn:sha1:7f87080d2e9744f67da17121363729c21cba4e53</id>
<content type='text'>
[ Upstream commit ee70b908f77a9d8f689dea986f09e6d7dc481934 ]

Property name "phy-3p0-supply" is used instead of "phy-reg_3p0-supply".

Fixes: 9f30b6b1a957 ("ARM: dts: imx: Add basic dtsi file for imx6sll")
cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Xu Yang &lt;xu.yang_2@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
</feed>
