From 9f29fbd33b73dafb7fca430d08e68b6b8f4bbb9d Mon Sep 17 00:00:00 2001
From: Dun Tan <dun.tan@intel.com>
Date: Thu, 25 Jul 2024 13:54:23 +0800
Subject: UefiCpuPkg: always create full mapping SMM page table

In this commit, we always create full mapping SMM page
table in SmmInitPageTable regardless the value of the
PcdCpuSmmRestrictedMemoryAccess.

Previously, when PcdCpuSmmRestrictedMemoryAccess is false,
only [0, 4G] is mapped in smm page table in SmmInitPageTable.
If the range above 4G is accessed in SMM, SmiPFHandler will
create new paging entry for the accessed range. To simplify
the code logic, we also create full mapping SMM page table
in SmmInitPageTable when PcdCpuSmmRestrictedMemoryAccess is
false. Then we don't need to dynamic create paging entry for
range above 4G except SMM profile is enabled.

The comparison of SMM page table before and after the change
under different configuration are listed here:
1.PcdCpuSmmRestrictedMemoryAccess is TRUE
     No change
2.PcdCpuSmmRestrictedMemoryAccess is FALSE and
  PcdCpuSmmProfileEnable is TRUE
     Before: the SMM page table when ReadyToLock covers
        1. SMRAM range 2.SMM profile range
        3. MMIO range below 4G
     After: the SMM page table when ReadyToLock covers
        1. SMRAM range 2.SMM profile range
        3. MMIO range below 4G and above 4G
3.PcdCpuSmmRestrictedMemoryAccess is FALSE and
  PcdCpuSmmProfileEnable is FALSE
     Before: the SMM page table when ReadyToLock covers
        [0, 4G]
     After: the SMM page table when ReadyToLock covers
        [0, MaxSupportPhysicalAddress]

Signed-off-by: Dun Tan <dun.tan@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c  | 8 ++------
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 5 +----
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index d18084b71f..6172c7df34 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -1,7 +1,7 @@
 /** @file
 Enable SMM profile.
 
-Copyright (c) 2012 - 2023, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2012 - 2024, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -616,11 +616,7 @@ InitPaging (
   PERF_FUNCTION_BEGIN ();
 
   PageTable = AsmReadCr3 ();
-  if (sizeof (UINTN) == sizeof (UINT32)) {
-    Limit = BASE_4GB;
-  } else {
-    Limit = (IsRestrictedMemoryAccess ()) ? LShiftU64 (1, mPhysicalAddressBits) : BASE_4GB;
-  }
+  Limit     = LShiftU64 (1, mPhysicalAddressBits);
 
   WRITE_UNPROTECT_RO_PAGES (WriteProtect, CetEnabled);
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 9052ea8e84..14b0b1981b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -201,7 +201,6 @@ SmmInitPageTable (
   UINT64                    *PdptEntry;
   UINT64                    *Pml4Entry;
   UINT64                    *Pml5Entry;
-  UINT8                     PhysicalAddressBits;
 
   //
   // Initialize spin lock
@@ -226,10 +225,8 @@ SmmInitPageTable (
 
   //
   // Generate initial SMM page table.
-  // Only map [0, 4G] when PcdCpuSmmRestrictedMemoryAccess is FALSE.
   //
-  PhysicalAddressBits = mCpuSmmRestrictedMemoryAccess ? mPhysicalAddressBits : 32;
-  PageTable           = GenSmmPageTable (mPagingMode, PhysicalAddressBits);
+  PageTable = GenSmmPageTable (mPagingMode, mPhysicalAddressBits);
 
   if (m5LevelPagingNeeded) {
     Pml5Entry = (UINT64 *)PageTable;
-- 
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