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path: root/MdePkg/Library/BaseLib
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2025-11-04MdePkg: Add code to detect running as an SEV guestRARelph4-0/+79
2025-09-26MdePkg: Remove ARM32 Support from BaseLibOliver Smith-Denny22-973/+5
2025-09-19MdePkg/Library/BaseLib: Remove __chkstk() from BaseLibMichael D Kinney3-20/+0
2025-06-05MdePkg: BaseLib: Add UUID-GUID conversion functionKun Qin2-0/+122
2024-11-01MdePkg: CodeQL Fixes.Michael Kubacki1-24/+40
2024-09-09MdePkg/BaseLib: Add NULL version Tdx functions for other architecturesCeping Sun1-0/+5
2024-08-30MdePkg: Rename the LoongArch CSR 0x20 registerChao Li1-12/+12
2024-08-06MdePkg/BaseLib: Add CRC16 CCITT False Implementation.kuqin121-0/+69
2024-08-01MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()Pierre Gondois3-0/+62
2024-08-01MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()Pierre Gondois3-1/+63
2024-07-17MdePkg/BaseLib: Optimize LOONGARCH64 csr usageDongyan Qian2-9/+7
2024-06-26MdePkg/BaseLib: Fix an instruction write width error in LoongArch64Dongyan Qian1-1/+1
2024-06-14MdePkg/X86UnitTestHost: set rdrand cpuid bitGerd Hoffmann1-1/+10
2024-06-12MdePkg/BaseLib: Let CpuDeadLoop() be breakable in debuggerRay Ni1-2/+4
2024-05-15MdePkg/BaseLib: Fix AARCH64 compilation errorShun Cheng Liu2-0/+2
2024-04-17MdePkg/BaseLib: Add a new VMGEXIT instruction invocation for SVSMTom Lendacky3-0/+135
2024-03-19MdePkg/BaseLib: Update TDVMCALL_EXPOSE_REGS_MASKCeping Sun1-1/+1
2024-02-06MdePkg: Add IOCSR operation for LoongArchChao Li2-0/+121
2024-02-06MdePkg: Add CSR operation for LoongArchChao Li3-0/+505
2024-02-06MdePkg: Add read stable counter operation for LoongArchChao Li2-0/+25
2024-02-06MdePkg: Add LoongArch Cpucfg functionChao Li2-0/+27
2024-02-06MdePkg: Add LoongArch64 local interrupt function set into BaseLibChao Li2-10/+34
2024-02-06MdePkg: Add LoongArch64 exception function set into BaseLibChao Li2-0/+42
2024-01-11MdePkg/BaseLib: Fix boot DxeCore hang on riscv platform王洋3-7/+63
2024-01-11MdePkg/BaseLib: RISC-V: Add function to update stimecmp registerSunil V L1-0/+7
2023-12-19MdePkg: Implement RISC-V Cache Management OperationsDhaval2-1/+18
2023-12-19MdePkg: Rename Cache Management Function To Clarify Fence Based OpDhaval1-4/+4
2023-12-03MdePkg/BaseLib: Fix CRC16-ANSI calculationPedro Falcato1-2/+2
2023-11-09MdePkg/BaseLib: Update TdVmcall to always output the value in R11Ceping Sun1-3/+1
2023-10-03MdePkg/BaseLib: fix typo in Arm SetJumpLeif Lindholm1-1/+1
2023-10-02MdePkg/BaseLib: ensure ARM LongJump never returns 0Leif Lindholm2-0/+4
2023-10-02MdePkg/BaseLib: correct register sizes in AArch64 SetJump/LongJumpLeif Lindholm2-8/+8
2023-10-02MdePkg/BaseLib: use normal register init in ARM SetJump implementationsLeif Lindholm2-2/+2
2023-10-02MdePkg/BaseLib: add ASSERT in ARM* SetJump implementationsLeif Lindholm2-0/+16
2023-10-02MdePkg/BaseLib: fix comments in ARM* SetJump/LongJump implementationsLeif Lindholm4-8/+4
2023-09-21RISCV: Fix InternalLongJump to return correct valueAndrei Warkentin1-5/+2
2023-07-15MdePkg/BaseLib: RISC-V: Support getting satp register valueTuan Phan1-0/+8
2023-06-06MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64Yong Li2-0/+35
2023-04-10MdePkg/Library/BaseLib: HOST_APPLICATION IA32/X64 onlyMichael D Kinney1-1/+1
2023-04-03MdePkg: Fix conditionally uninitialized variablesMichael Kubacki1-8/+32
2023-03-30MdePkg/BaseLib AARCH64: Make asm files BTI compatibleArd Biesheuvel8-0/+10
2023-03-30MdePkg/BaseLib AARCH64: Make LongJump() BTI compatibleArd Biesheuvel1-2/+1
2023-03-17MdePkg: Update code to be more C11 compliant by using __func__Rebecca Cran1-1/+1
2023-03-08MdePkg: BaseLib: don't log in RISCV InternalSwitchStackAndrei Warkentin1-8/+0
2023-02-16MdePkg/BaseLib: RISC-V: Add few more helper functionsSunil V L5-4/+129
2022-12-14MdePkg/UnitTestHostBaseLib: Remove HOST_APPLICATION limitationLiu, Zhiguang1-3/+6
2022-11-07MdePkg/BaseLib: Fix out-of-bounds reads in SafeStringPedro Falcato1-4/+21
2022-10-14MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture.Chao Li11-1/+339
2022-06-13MdePkg/BaseLib: Add CRC16-ANSI and CRC32c implementationsPedro Falcato1-0/+144
2022-05-13MdePkg: Remove RVCT supportRebecca Cran2-19/+0
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