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Bumps [github/codeql-action](https://github.com/github/codeql-action) from 3 to 4.
- [Release notes](https://github.com/github/codeql-action/releases)
- [Changelog](https://github.com/github/codeql-action/blob/main/CHANGELOG.md)
- [Commits](https://github.com/github/codeql-action/compare/v3...v4)
---
updated-dependencies:
- dependency-name: github/codeql-action
dependency-version: '4'
dependency-type: direct:production
update-type: version-update:semver-major
...
Signed-off-by: dependabot[bot] <support@github.com>
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Ref:[059332b]
Rootcause: The SectionLength was incorrectly computed using
the FFS_FILE_SIZE() macro. This macro operates on the
EFI_FFS_FILE_HEADER structure, which is incompatible with the
SECTION_SIZE header format.
This mismatch introduces a potential defect due to inaccurate
section size calculation.
Solution: To ensure correctness and structural alignment,
SectionLength must be computed using the SECTION_SIZE macro
defined in MdePkg\Include\Pi\PiFirmwareFile.h.
This macro performs size extraction using byte-wise access.
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Gowtham M <gowthamm@ami.com>
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The current implementation from Dxe/Image/Image.c does not handle the
configuration where there might be multiple MemoryAllocationModules.
Given that the `ModuleName` is included in the hob data and used for
targetting the consumer, DXE core should specify the GUID when looking up
for its own MemoryAllocationModule.
This change adds a check to ensure the located hob is targetting DXE
core.
Signed-off-by: Kun Qin <kuqin12@gmail.com>
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# Description
Update brotli from v1.0.9 to v1.2.0
https://github.com/google/brotli/releases/tag/v1.2.0
- [ ] Breaking change?
- **Breaking change** - Does this PR cause a
break in build or boot behavior?
- Examples: Does it add a new library class
or move a module to a different repo.
- [x] Impacts security?
- **Security** - Does this PR have a direct security impact?
- Fixes CVE-2025-6176 reported in brotli < 1.2.0.
- [ ] Includes tests?
- **Tests** - Does this PR include any explicit test code?
- Examples: Unit tests or integration tests.
## How This Was Tested
Verified booting on a virtual platform by
compressing/decompressing PEI/DXE sections.
## Integration Instructions
NA
Signed-off-by: Vineel Kovvuri[MSFT] <vineelko@microsoft.com>
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# Description
Update brotli from v1.0.9 to v1.2.0
https://github.com/google/brotli/releases/tag/v1.2.0
- [ ] Breaking change?
- **Breaking change** - Does this PR cause a
break in build or boot behavior?
- Examples: Does it add a new library class
or move a module to a different repo.
- [x] Impacts security?
- **Security** - Does this PR have a direct security impact?
- Fixes CVE-2025-6176 reported in brotli < 1.2.0.
- [ ] Includes tests?
- **Tests** - Does this PR include any explicit test code?
- Examples: Unit tests or integration tests.
## How This Was Tested
Verified booting on a virtual platform by
compressing/decompressing PEI/DXE sections.
## Integration Instructions
NA
Signed-off-by: Vineel Kovvuri[MSFT] <vineelko@microsoft.com>
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RootCause: SectionSize, SectionLength and FileLength are declared as
UINTN, UINTN and UINT32 but are typecast to UINT32 and masked
with 0x00FFFFFF to store only the lower 24 bits.
Although this approach yields the correct result,
it introduces a potential security vulnerability due to
unsafe typecasting and dereferencing.
Solution: Using the predefined macro FFS_FILE_SIZE()
from MdePkg\Include\Pi\PiFirmwareFile.h,
which safely performs the same operation by reconstruct
the size using individual byte access.
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Gowtham M <gowthamm@ami.com>
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Confidential computing guests do not support MTRR emulation.
This is as true for AMD SEV as it is for Intel's Tdx.
Signed-off-by: Richard Relph <richard.relph@amd.com>
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Similar to Intel's Tdx, we need a mechanism to detect running as
an AMD SEV guest that will work in all phases everywhere. This
will be immediately used to prevent usage of MTRRs with SEV guests.
Signed-off-by: Richard Relph <richard.relph@amd.com>
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Added IPMI boot initiator mailbox define for the block data size.
Signed-off-by: Brit Chesley <brit.chesley@amd.com>
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Parse the ELF file for RISC-V Zicfilp extension support to identify
forward control flow integrity (FCFI) features.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
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REF: UEFI spec v2.10 23.1.2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4660
1.For EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImage():
Add the following sentence at the end of the Image parameter
description. "May be NULL with a zero ImageSize in order to determine
the size of the buffer needed".
Modify the description of "EFI_INVALID_PARAMETER" return code as "The
ImageSize is not too small and Image is NULL."
2.For EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo():
Add the following sentence at the end of the ImageInfo parameter
description."May be NULL with a zero ImageInfoSize in order to
determine the size of the buffer needed".
Modify the description of "EFI_INVALID_PARAMETER" return code as "The
ImageInfoSize is not too small and Image is NULL." and add new
descriptions for "EFI_INVALID_PARAMETER" return code.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Yi Li <yi1.li@intel.com>
Signed-off-by: Pethaiyan Madhan <madhan.pethaiyan@intel.com>
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Add the INF file of AmdStandaloneMmCpuFeaturesLib for AMD family, which
supports building the SmmCpuFeaturesLib code for Standalone MM. It is
based on the existing file, StandaloneMmCpuFeaturesLib.inf. Minimal code
changes are also made to allow reuse of existing code for Standalone MM.
Signed-off-by: Phil Noh <Phil.Noh@amd.com>
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According to the implementation of `HiiGetSupportedLanguages`, the caller
is responsible for freeing the returned string using FreePool().
Signed-off-by: Qihang Gao <gaoqihang@loongson.cn>
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Ensures the Snp Structure is initialized as NULL.
Signed-off-by: Eeshan Londhe <eeshanlondhe@microsoft.com>
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If a secure partition on AArch64 platforms would consume extended time
to operate with peripherals, it might elect to yield the control back to
normal world and expect the normal world to callback after hinted period
of time.
This change adds the FFA_YIELD handling from ArmFfaLib to support long
operations from secure partitions. Timeout arguments are ignored because
systems in this context cannot benefit from the timeout period. Treating
FFA_YIELD like FFA_INTERRUPT and expecting the caller to invoke FFA_RUN
is the least disruptive approach while achieving the intended behavior.
This was tested on proprietary hardware platforms and booted to Windows.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
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current Linux auto test OS did not support python tkinter
feature, but windows auto test system supported it as default,
so add a check for it.
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ted Kuo <ted.kuo@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
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The current algorithm evaluates page protection in
sections of a PE/COFF image at DWORD granularity and
it skips the evaluation of the first DWORD of the
PE/COFF image.
If a PE/COFF section has a VirtualSize that is ends
in first 4 bytes of a 4KB page, then the PE/COFF
section protection attributes for that section are
not applied to that page due to the DWORD stride.
For example, a .text section with a VirtualSize of
0x1001, 0x1002, 0x1003, or 0x1004 followed by non
.text section will not apply the PAGE_EXECUTE_READ
attribute to the second page of the .text section
and execution of code at the end of that .text
section generates an access violation exception.
The fix is to change the stride for evaluating page
protection attributes from DWORD to BYTE.
The loop is also updated to include evaluation of
the first DWORD of the PE/COFF image.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
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Previously register x6 was used to temporarily hold the transfer list
address before the stack was setup and the jump to C code.
This however is not working for RPi3, platform code uses w6 which
aliases x6 causing overwrites.
Instead we now use TPIDRRO_EL0 to temporarily hold the value.
This is inspired by PEI using TPIDR_EL0 to store the PEI services
table pointer.
Signed-off-by: Prachotan Bathi <prachotan.bathi@arm.com>
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Expand EnrollDefaultKeys by adding the 2023 Microsoft Secure Boot
keys to the existing keys already being enrolled.
Signed-off-by: Alex Haydock <alex@alexhaydock.co.uk>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors has been
dropped, the instances of DXE_SAL_DRIVER have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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The DXE_SAL_DRIVER module type was introduced to support
Itanium (IPF) platforms. Since support for Itanium processors
has been dropped, the instances of DXE_SAL_DRIVER
have been removed.
Ref: [3cb0a311cb7e747d7be5c5076d0fff76ad256d2b]
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Sathya Ravichandran <sathyar@ami.com>
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FvLib is moving from StandaloneMmPkg to MdePkg. FvLib is already
included from MdeLibs.dsc.inc. So, just remove the usage of FvLib
from StandaloneMmPkg.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
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FSP Spec says: "The FSP is not Position Independent Code (PIC) and
each FSP component has to be rebased if it is placed at a location
which is different from the preferred base address specified during
the FSP build."
Normally, the FSP location in flash is the same preferred base
address specified during the FSP build. To avoid FSP-S and FSP-I
running directly from flash, platform may copy the FSP binaries into
physical memory. This causes FSP location to be different from the
preferred base address.
To support this, this commit checks the Image Base from FSP header
and the FSP base address PCD. If these two are different, This commit
assumes the FSP is copied into physical memory and FSP location is
changed. In such scenario, the commit will rebase the FSP to the address
provided by the PCD.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
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Copy FvLib from StandaloneMmPkg to MdePkg because it is a common library.
Future steps will include:
1. Modify platform code including Edk2Platforms repo to use FvLib from MdePkg.
2. Remove FvLib from StandaloneMmPkg
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
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PR #11443 introduced a regression by adding a DEBUG() message
when the lock for events is acquired and that lock is at
TPL_HIGH_LEVEL. If DEBUG() messages are routed through Report
Status Code, and the Report Status Code Protocol has not been
located yet, then a call to gBS->LocateProtocol() is made and
that call raises TPL to TPL_NOTIFY which causes a TPL inversion.
The event lock is used to atomically update gEventSignalQueue.
There is no need for the DEBUG() message to within the event
lock scope.
The fix is to scope the event lock to only the InsertHeadList()
call to update gEventSignalQueue.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
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CPB, DB, and CDB structs to use DMA-able memory.
Updates the overall SNP_DRIVER allocation to use AllocatePool() instead of PciIo->AllocateBuffer(). This moves this struct out of DMA-able memory.
Allocates the PXE_CDB struct as a pointer instead, using PciIo->AllocateBuffer() for DMA-able memory.
End result:
CPB, DB, and CDB are allocated with individual PciIo->AllocateBuffer() calls with a size of 4096 for CPB and DB. and sizeof(PXE_CDB) for CDB.
Each of these members point to locations within the Allocated Buffer, and all of these pointers are at-least
8-Byte aligned.
SNP_DRIVER is allocated with AllocatePool()
In the SNP_DRIVER structure, the PXE_CDB member is changed to a pointer so we can allocate it with PciIo->AllocateBuffer()
Signed-off-by: Eeshan Londhe <eeshanlondhe@microsoft.com>
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Fix the coverity warnings reported in the CryptoPkg.
Signed-off-by: Kanagavel S <kanagavels@ami.com>
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Added debug trace messages on LocateProtocol failure for
gEfiDxeSmmReadyToLockProtocolGuid. Returned device error in case of
EfiCreateProtocolNotifyEvent failure.
Removed ASSERT due to if condition.
Signed-off-by: Arun Subramanian Baskaran <arun.subramanian.baskaran@intel.com>
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In StandaloneMmPkg/Core/Dispatcher.c, a comment referred to SMRAM.
SMRAM is specific to the x86 architecture.
The StandaloneMmPkg is designed to be architecture-agnostic.
This commit updates the comment to use the more generic term MMRAM
(Management Mode RAM) to better reflect the nature of the package.
Signed-off-by: Damien Chen <inkfan130924783@gmail.com>
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Memory Attributes Table needs to be updated to contain executable
permissions for UEFI runtime drivers loaded after EndOfDxe.
Fixes a regression introduced by bb248a9.
Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com>
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Add the missing parser for EArchCommonObjTpm2DeviceInfo.
This missing parser causing assert for EArchCommonObjMcfgPciConfigSpaceInfo
and EArchCommonObjPciRootPortInfo parser.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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This change introduces support for root port devices and their
corresponding _PRT (PCI Routing Table) entries in the PCIe SSDT.
Updates the PCIe SSDT generator to detect and use the root port token.
When available, the generator reads the configuration and creates device
entries with appropriate _PRT tables.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Adds RootPortInfoToken to PCIe config space object to
support addition of root port devices in PCIE SSDT.
Updates the ConfigurationManagerObjectParser to include the new token.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Introduce new architecture common namespace object
for PCIe root ports in the DynamicTables package.
This object holds information:
- PCIe root port address in device and function format
- Reference token information to the PCIe routing table object
- Slot number information for the root port
Also updates ConfigurationManagerObjectParser to parse
the new object and populate the relevant fields.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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- Adds AcpiMcfgLib library to X64 DynamicTableFactoryDxe
- Adds AcpiSpcrLib library to X64 DynamicTableFactoryDxe
- Adds AcpiSsdtPcieLib library to X64 DynamicTableFactoryDxe
- Rearrage the libraries in alphabetical order
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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X64 platforms supports WordIo and uncached PCIe resources.
Hence, include WordIo and uncached PCIe resources in _CRS.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Following the APs now always initializing separate exception
stacks, this commit always initializes a separate exception
stack for the BSP as well. Previously, this was only enabled
when PcdCpuStackGuard was set.
However, even when a stack guard page is not present,
stack overflows can still occur and corrupt the stack; if an
exception is taken here, it is still valuable to have a separate
exception stack for sanity.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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Currently, CpuExceptionHandlerLibNull returns EFI_UNSUPPORTED for
InitializeSeparateExceptionStacks. However, CpuMpPei, CpuDxe, and
DXE Core are all moving to call this function unconditionally and
expect it returns success. As such, the null lib is updated to
return success.
This fixes a hang on EmulatorPkg where DXE Core asserts if this
function returns an error.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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TR is used to enable a separate safe stack when a stack overflow occurs.
When PEI starts up the APs, TR is non-zero and so each processor has its
own GDT. TR is an offset into the GDT and so points to a different TSS
entry in each AP.
There is a small window in early DXE after MpInitLibInitialize() is
called where:
- TR is non-zero because it has been inherited from the PEI phase
- TR is not restored to 0
- The APs are all switched to using the BSP's GDT
- SaveVolatileRegisters() is called from ApWakeupFunction() before the
APs go to sleep, which saves the non-zero TR value to
CpuMpData->CpuData[].VolatileRegisters.Tr, cause TR to point to the
same TSS entry in the BSP's GDT
- The next time the APs are woken up, RestoreVolatileRegisters() is
called from ApWakeupFunction() which would attempt to load the non-zero
TR value into the actual task register, which creates a race condition
to a #GP fault because loading the task register sets the busy bit in
the TSS descriptor and a #GP fault occurs if the busy bit is already
set when loading the task register.
To avoid this issue, the task register is only loaded if TR is non-zero
and the TSS descriptor is valid and not busy. HW sets the busy bit and
does not clear it. edk2 does not clear the busy bit, so the BSP's TSS
descriptor will be marked busy forever and the APs will not load the
task register until they have their own GDT/TSS set up.
Co-authored-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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Today, CpuMpPei and CpuDxe only initialize separate exception
stacks for the APs when PcdCpuStackGuard is enabled so that
if a stack overflow occurs, hitting the guard page, the exception
can be handler with a separate stack.
However, this operation also creates a separate GDT for each AP.
This is a safer option than all APs sharing the BSP's GDT because
there are issues with concurrent access to the structures contained
within. Furthermore, even when a stack guard page is not present,
stack overflows can still occur and corrupt the stack; if an
exception is taken here, it is still valuable to have a separate
exception stack for sanity.
This commit updates CpuMpPei and CpuDxe to always create separate
exception stacks for the APs (and therefore separate GDTs).
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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`PageStartAddress` variable was not set correctly because the encryption bit
was not considered, which broke the page walk logic.
Get the bitmask and mask the encryption bit.
Signed-off-by: Luigi Leonardi <leonardi@redhat.com>
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Improving InitializeAcpiTableDxe() behavior.
Signed-off-by: George Liao <george.liao@intel.com>
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Added "PublishTables()" and "SdtNotifyAcpiList()" for completing
AddTableToList behavior in the InstallAcpiTableFromAcpiSiliconHob().
Signed-off-by: George Liao <george.liao@intel.com>
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