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<title>Tianocore/edk2.git/OvmfPkg/Library/BaseMemEncryptSevLib, branch dependabot/github_actions/actions/github-script-8</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fgithub-script-8</id>
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<updated>2025-09-09T18:49:32+00:00</updated>
<entry>
<title>OvmfPkg: Remove OVMF IA32</title>
<updated>2025-09-09T18:49:32+00:00</updated>
<author>
<name>Oliver Smith-Denny</name>
<email>osde@microsoft.com</email>
</author>
<published>2025-08-25T18:24:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=1fb88ffe284782cc79e306306b8d19829b6248b7'/>
<id>urn:sha1:1fb88ffe284782cc79e306306b8d19829b6248b7</id>
<content type='text'>
This commit removes OVMF IA32 from edk2 per RFC
https://edk2.groups.io/g/devel/topic/rfc_remove_ovmf_ia32_and/114152215.

OVMF IA32 is a 32 bit only platform that no longer represents the vast
majority of physical platforms. The RFC details more reasoning in
much more depth.

OVMF IA32 will be kept in a branch off the edk2-stable202508 tag for
any long term consumers; it will receive build break updates only
(e.g. if an upstream submodule changes location).

Signed-off-by: Oliver Smith-Denny &lt;osde@microsoft.com&gt;
</content>
</entry>
<entry>
<title>OvmfPkg/MemEncryptSevLib: Check if SEV-SNP coherency mitigitation is needed</title>
<updated>2025-09-09T17:43:31+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2025-07-22T20:06:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=20f24c0f67b3364cd590e1eea470f74be40e7710'/>
<id>urn:sha1:20f24c0f67b3364cd590e1eea470f74be40e7710</id>
<content type='text'>
CPUID bit Fn8000001F_EBX[31] defines the COHERNECY_SFW_NO CPUID bit that,
when set, indicates that the software mitigation for this vulnerability is
not needed.

Add support to check for this CPUID bit and avoid the mitigation if set.

Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
</content>
</entry>
<entry>
<title>OvmfPkg/MemEncryptSevLib: Evict cache lines during SNP memory validation</title>
<updated>2025-09-09T17:43:31+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2025-08-12T19:43:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=3b0d834db286a236fd22c41923fc271fc44ead5f'/>
<id>urn:sha1:3b0d834db286a236fd22c41923fc271fc44ead5f</id>
<content type='text'>
An SNP cache coherency vulnerability may require a mitigation to evict
cache lines after memory has been validated. Perform this mitigation
after having validated memory.

CVE-2024-36331

Signed-off-by: Michael Roth &lt;michael.roth@amd.com&gt;
Co-developed-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;</content>
</entry>
<entry>
<title>OvmfPkg: Enable AMD SEV-ES DebugVirtualization</title>
<updated>2024-07-04T20:39:26+00:00</updated>
<author>
<name>Alexey Kardashevskiy</name>
<email>aik@amd.com</email>
</author>
<published>2024-05-28T04:48:40+00:00</published>
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<id>urn:sha1:28099661893327296e18b8f98a1e7c3e757c7d49</id>
<content type='text'>
Write the feature bit into PcdConfidentialComputingGuestAttr
and enable DebugVirtualization in PEI, SEC, DXE.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Reviewed-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Alexey Kardashevskiy &lt;aik@amd.com&gt;
---
Changes:
v5:
* "rb" from Tom

v4:
* s/DebugSwap/DebugVirtualization/g
</content>
</entry>
<entry>
<title>OvmfPkg: Add AMD SEV-ES DebugVirtualization feature support</title>
<updated>2024-07-04T20:39:26+00:00</updated>
<author>
<name>Alexey Kardashevskiy</name>
<email>aik@amd.com</email>
</author>
<published>2022-11-30T08:41:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=9f06feb5d2fa43e184690034e70e6d427cf6913d'/>
<id>urn:sha1:9f06feb5d2fa43e184690034e70e6d427cf6913d</id>
<content type='text'>
The SEV-ES DebugVirtualization feature enables type B swapping of
debug registers on #VMEXIT and makes #DB and DR7 intercepts
unnecessary and unwanted.

When DebugVirtualization is enabled, this stops booting if
interaction from the HV.

Add new API to PEI, SEC, DXE.

This does not change the existing behaviour yet.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Reviewed-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Alexey Kardashevskiy &lt;aik@amd.com&gt;
---
Changes:
v5:
* "rb" from Tom

v4:
* s/DebugSwap/DebugVirtualization/
</content>
</entry>
<entry>
<title>OvmfPkg/BaseMemEncryptLib: Check for presence of an SVSM when not at VMPL0</title>
<updated>2024-04-17T20:04:41+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2024-03-08T15:33:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=0afb8743493853e30171f6000de51242e22a1eb8'/>
<id>urn:sha1:0afb8743493853e30171f6000de51242e22a1eb8</id>
<content type='text'>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654

Currently, an SEV-SNP guest will terminate if it is not running at VMPL0.
The requirement for running at VMPL0 is removed if an SVSM is present.

Update the current VMPL0 check to additionally check for the presence of
an SVSM is the guest is not running at VMPL0.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Laszlo Ersek &lt;lersek@redhat.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Acked-by: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
</content>
</entry>
<entry>
<title>OvmfPkg/BaseMemEncryptSevLib: Maximize Page State Change efficiency</title>
<updated>2024-04-17T20:04:41+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2024-03-08T15:32:32+00:00</published>
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<id>urn:sha1:18fdffe825683df40d7a4a9eba11b8630bcef050</id>
<content type='text'>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654

Similar to the Page State Change optimization added previously, also take
into account the possiblity of using the SVSM for PVALIDATE instructions.
Conditionally adjust the maximum number of entries based on how many
entries the SVSM calling area can support.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Laszlo Ersek &lt;lersek@redhat.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Acked-by: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
</content>
</entry>
<entry>
<title>OvmfPkg/BaseMemEncryptSevLib: Use AmdSvsmSnpPvalidate() to validate pages</title>
<updated>2024-04-17T20:04:41+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2024-03-08T15:32:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=f6bf37c1711c07709b0817a996c5b5a97f263bdd'/>
<id>urn:sha1:f6bf37c1711c07709b0817a996c5b5a97f263bdd</id>
<content type='text'>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654

The PVALIDATE instruction is used to change the SNP validation of a page,
but that can only be done when running at VMPL0. To prepare for running at
a less priviledged VMPL, use the AmdSvsmLib library API to perform the
PVALIDATE. The AmdSvsmLib library will perform the proper operation on
behalf of the caller.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Laszlo Ersek &lt;lersek@redhat.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Acked-by: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
</content>
</entry>
<entry>
<title>OvmfPkg/BaseMemEncryptSevLib: Maximize Page State Change efficiency</title>
<updated>2024-04-17T18:30:03+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2024-03-08T15:31:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=069f9911a35c6191ea0cace0b5b5c8061e9b7720'/>
<id>urn:sha1:069f9911a35c6191ea0cace0b5b5c8061e9b7720</id>
<content type='text'>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654

When building the Page State Change entries for a range of memory, it can
happen that multiple calls to BuildPageStateBuffer() need to be made. If
the size of the input work area passed to BuildPageStateBuffer() exceeds
the number of entries that can be passed to the hypervisor using the GHCB
shared buffer, the Page State Change VMGEXIT support will issue multiple
VMGEXITs to process all entries in the buffer.

However, it could be that the final VMGEXIT for each round of Page State
Changes is only for a small number of entries and subsequent VMGEXITs may
still be issued to handle the full range of memory requested. To maximize
the number of entries processed during the Page State Change VMGEXIT,
limit BuildPageStateBuffer() to not build entries that exceed the maximum
number of entries that can be handled in a single Page State Change
VMGEXIT.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Laszlo Ersek &lt;lersek@redhat.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Reviewed-by: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
</content>
</entry>
<entry>
<title>OvmfPkg/BaseMemEncryptSevLib: Re-organize page state change support</title>
<updated>2024-04-17T18:30:03+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2024-03-08T15:31:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=2b330b57dbe8014c5fa9f10d4cf4ae5923e3b143'/>
<id>urn:sha1:2b330b57dbe8014c5fa9f10d4cf4ae5923e3b143</id>
<content type='text'>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654

In preparation for running under an SVSM at VMPL1 or higher (higher
numerically, lower privilege), re-organize the way a page state change
is performed in order to free up the GHCB for use by the SVSM support.

Currently, the page state change logic directly uses the GHCB shared
buffer to build the page state change structures. However, this will be
in conflict with the use of the GHCB should an SVSM call be required.

Instead, use a separate buffer (an area in the workarea during SEC and
an allocated page during PEI/DXE) to hold the page state change request
and only update the GHCB shared buffer as needed.

Since the information is copied to, and operated on, in the GHCB shared
buffer this has the added benefit of not requiring to save the start and
end entries for use when validating the memory during the page state
change sequence.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Erdem Aktas &lt;erdemaktas@google.com&gt;
Cc: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Laszlo Ersek &lt;lersek@redhat.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Cc: Min Xu &lt;min.m.xu@intel.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Acked-by: Gerd Hoffmann &lt;kraxel@redhat.com&gt;
</content>
</entry>
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