Tianocore/edk2.git/MdePkg/Include/Register, branch dependabot/github_actions/github/codeql-action-4EDK II (mirror)https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Fgithub%2Fcodeql-action-42025-09-09T17:43:31+00:00MdePkg: Add the COHERENCY_SFW_NO CPUID bit field2025-09-09T17:43:31+00:00Tom Lendackythomas.lendacky@amd.com2025-07-22T21:59:44+00:00urn:sha1:07ba06fdf7c3e6314aa8b3d7341e7910a469dbb2
Update the CPUID 0x8000001F EBX definition to add the COHERENCY_SFW_NO
bit field. The COHERENCY_SFW_NO bit is used to indicate that the SEV-SNP
cache coherency mitigation is not needed.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
MdePkg/AmdSev: Add SVSM protocol vTPM call numbers2025-03-16T19:21:44+00:00Oliver Steffenosteffen@redhat.com2024-12-11T10:17:07+00:00urn:sha1:70f806ec23fb1c376afe33f2f054819a03e21641
Add call numbers for the SVSM vTPM protocol, as defined in the "Secure
VM Service Module for SEV-SNP Guests" Publication # 58019 Revision: 1.00
Signed-off-by: Oliver Steffen <osteffen@redhat.com>
MdePkg/AmdSev: Add SVSM protocol call numbers2025-03-16T19:21:44+00:00Oliver Steffenosteffen@redhat.com2024-12-11T10:07:48+00:00urn:sha1:fa74200c92693add490b18615c2821ba72a2d58d
Add protocol and call numbers as defined in the "Secure VM Service
Module for SEV-SNP Guests" Publication # 58019 Revision: 1.00
https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/specifications/58019.pdf
Signed-off-by: Oliver Steffen <osteffen@redhat.com>
MdePkg: Added definition of AMD specific public MSRs2024-11-12T01:07:12+00:00Kun Qinkuqin@microsoft.com2021-08-20T20:49:04+00:00urn:sha1:961a9e1d76cdb3a56ac2eecc480492c18c1ab927
Added definition of AMD specific public MSRs:
1. SMBASE
2. SMM_ADDR
3. SMM_MASK
Signed-off-by: Kun Qin <kuqin@microsoft.com>
MdePkg/BaseLib: RISC-V: Add FPU CSR constants2024-10-04T04:53:21+00:00Heinrich Schuchardtheinrich.schuchardt@canonical.com2024-09-16T21:08:06+00:00urn:sha1:28dd588ca80c61c4bea9294785d5d884ad3f2c41
* Define CSR fcsr
* Define bitmasks for vs and fs bit fields in the mstatus register
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
MdePkg: Remove the old name of LoongArch CSR 0x202024-08-30T19:54:01+00:00Chao Lilichao@loongson.cn2024-08-29T07:56:55+00:00urn:sha1:f6092b5e2be20139393a58bf454fb000020a3918
Since all places where the old name was used for the LoongArch CSR 0x20
regiser have been changed to the new name, the old name is removed.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
MdePkg: Rename the LoongArch CSR 0x20 register2024-08-30T19:54:01+00:00Chao Lilichao@loongson.cn2024-08-29T07:24:53+00:00urn:sha1:a066ca16d348122b160b407008d77ea6329fe6f3
Added a new name for CSR 0x20 because LoongArch SPEC has adjustd the CSR
0x20 register name.
Ref: LoongArch Reference Manual Vol 1, Seciton 7.1.
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
MdePkg/Library: Add RISCV64 support to BaseRngLib2024-07-15T04:05:56+00:00Dhavaldhaval@rivosinc.com2024-06-20T12:12:41+00:00urn:sha1:b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf
The ratified RISC-V crypto scalar extensions provide entropy bits via the
seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified
and provides 16 bits of entropy seed when reading the SEED CSR.
Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be
accumulated from the `seed` CSR. This driver is based on the driver in
the Linux kernel.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
MdePkg/StmApi.h: Add SMM_REV_ID definition for STM header2024-07-12T03:40:55+00:00Michael Kubackimichael.kubacki@microsoft.com2024-07-12T00:55:30+00:00urn:sha1:72d6e247b781cca65aac71c97c5094650b003a9d
The `SMM_REV_ID` is defined in the STM specification:
https://www.intel.com/content/www/us/en/content-details/671521/smi-transfer-monitor-stm-developer-or-user-guide.html?wapkw=stm,
section 10.1.1.
This adds it into the `StmApi.h` for potential STM usage.
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
MdePkg/Register/Amd: Define all bits from MSR_SEV_STATUS_REGISTER2024-07-04T20:39:26+00:00Alexey Kardashevskiyaik@amd.com2022-11-22T02:18:41+00:00urn:sha1:bc3a1ec2a2838f596678ddd247d10332c6790dab
For now we need DebugSwap but others are likely to be needed too.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
Changes:
v5:
* "rb" from Tom
v4:
* added more from April/2024 APM