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<title>Tianocore/edk2.git/MdeModulePkg/MdeModulePkg.dec, branch trunk</title>
<subtitle>EDK II (mirror)</subtitle>
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<updated>2024-06-04T03:43:08+00:00</updated>
<entry>
<title>Renormalized end-of-lines from master@27b044605cd5f6b33a3d231576003850b3fe305b</title>
<updated>2024-06-04T03:43:08+00:00</updated>
<author>
<name>kx</name>
<email>kx@radix.pro</email>
</author>
<published>2024-06-04T03:43:08+00:00</published>
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<id>urn:sha1:7e2ccccace24636f29ddc210b94606abd4c7e42b</id>
<content type='text'>
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</entry>
<entry>
<title>MdeModulePkg:BaseSpiHcPlatformLib: Adding NULL lib instance</title>
<updated>2024-05-08T04:43:58+00:00</updated>
<author>
<name>Brit Chesley</name>
<email>brit.chesley@amd.com</email>
</author>
<published>2024-04-29T20:50:53+00:00</published>
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<id>urn:sha1:5590cefe93d02f52be8de8eef96c35a2f4d1ba0a</id>
<content type='text'>
Adding NULL SpiHcPlatformLib instance. This library is responsible for
handling the low level details of the SPI host controller. Since this is
platform specific this library will be dependent on OEM SPI
implementation. The SPI host controller layer will utilize this library
for SPI bus transactions.

Bugzilla #4753

Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Abner Chang &lt;abner.chang@amd.com&gt;
Cc: Abdul Lateef Attar &lt;AbdulLateef.Attar@amd.com&gt;
Signed-off-by: Brit Chesley &lt;brit.chesley@amd.com&gt;
Acked-by: Abner Chang &lt;abner.chang@amd.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Add PCD for the delay of HCRST</title>
<updated>2024-05-07T04:48:09+00:00</updated>
<author>
<name>Xianglei Cai</name>
<email>xianglei.cai@intel.com</email>
</author>
<published>2024-05-07T01:15:51+00:00</published>
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<id>urn:sha1:1c0d4ae2c0fd24164873947c2e262c499ecf13b5</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=4727

Recently some of XHCI host controllers require to have
extra 1ms delay before accessing any MMIO register
during reset. PHY transition from P3 to P0 can take
around 1.3ms and the xHCI reset can take around 1.5ms.
Add PCD to control the delay, the default is 2 ms.

Cc: Ray Ni                   &lt;ray.ni@intel.com&gt;
Cc: Liming Gao               &lt;gaoliming@byosoft.com.cn&gt;
Cc: Krzysztof Lewandowski    &lt;krzysztof.lewandowski@intel.com&gt;
Cc: Jenny Huang              &lt;jenny.huang@intel.com&gt;
Cc: More Shih                &lt;more.shih@intel.com&gt;
Cc: Ian Chiu                 &lt;ian.chiu@intel.com&gt;
Signed-off-by: Xianglei Cai &lt;xianglei.cai@intel.com&gt;
Reviewed-by: Krzysztof Lewandowski &lt;krzysztof.lewandowski@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Variable: Add TCG SPDM device measurement update</title>
<updated>2024-04-30T02:21:13+00:00</updated>
<author>
<name>Wenxing Hou</name>
<email>wenxing.hou@intel.com</email>
</author>
<published>2024-04-18T09:28:13+00:00</published>
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<id>urn:sha1:d8e4c4b000e1bfc691271239e46803585975d715</id>
<content type='text'>
Add EV_EFI_SPDM_DEVICE_POLICY support for MeasureVariable.

Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Signed-off-by: Wenxing Hou &lt;wenxing.hou@intel.com&gt;
Reviewed-by: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: Add definitions in DEC for SPI NOR Flash SFDP driver</title>
<updated>2024-04-20T08:26:40+00:00</updated>
<author>
<name>Abner Chang</name>
<email>abner.chang@amd.com</email>
</author>
<published>2023-08-13T04:17:02+00:00</published>
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<id>urn:sha1:6dc09fda0484a4404cca2432a64ec8368d2f9424</id>
<content type='text'>
BZ#: 4473

Signed-off-by: Abner Chang &lt;abner.chang@amd.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Jian J Wang &lt;jian.j.wang@intel.com&gt;
Cc: Abdul Lateef Attar &lt;abdattar@amd.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Reviewed-by: Abdul Lateef Attar &lt;abdattar@amd.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/AcpiTableDxe: PCD switch to avoid using ACPI reclaim memory</title>
<updated>2024-04-09T07:03:08+00:00</updated>
<author>
<name>Aaron Li</name>
<email>aaron.li@intel.com</email>
</author>
<published>2024-03-26T07:57:33+00:00</published>
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<id>urn:sha1:932db9df0caa26daca4edf133fb2aed7b4a9193e</id>
<content type='text'>
UEFI spec defined ACPI Tables at boot time can be contained in memory of
type EfiACPIReclaimMemory or EfiAcpiMemoryNVS, although InstallAcpiTable
with AcpiTableProtocol will only allocate memory with type
EfiACPIReclaimMemory (Except FACS).

This patch provides an optional method controlled by PCD to avoid using
EfiACPIReclaimMemory, by setting the PCD PcdNoACPIReclaimMemory to TRUE,
all ACPI allocated memory will use EfiAcpiMemoryNVS instead.

Cc: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
Cc: Dandan Bi &lt;dandan.bi@intel.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Liu Yun &lt;yun.y.liu@intel.com&gt;
Cc: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Aaron Li &lt;aaron.li@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Reviewed-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: DxeCore: Do Not Apply Guards to Unsupported Types</title>
<updated>2024-03-14T16:29:22+00:00</updated>
<author>
<name>Oliver Smith-Denny</name>
<email>osde@linux.microsoft.com</email>
</author>
<published>2024-03-09T19:06:03+00:00</published>
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<id>urn:sha1:e7486b50646d6a645706b61d2f8d74b3dca23ce0</id>
<content type='text'>
Currently, there are multiple issues when page or pool guards are
allocated for runtime memory regions that are aligned to
non-EFI_PAGE_SIZE alignments. Multiple other issues have been fixed for
these same systems (notably ARM64 which has a 64k runtime page
allocation granularity) recently. The heap guard system is only built to
support 4k guard pages and 4k alignment.

Today, the address returned to a caller of AllocatePages will not be
aligned correctly to the runtime page allocation granularity, because
the heap guard system does not take non-4k alignment requirements into
consideration.

However, even with this bug fixed, the Memory Allocation Table cannot be
produced and an OS with a larger than 4k page granularity will not have
aligned memory regions because the guard pages are reported as part of
the same memory allocation. So what would have been, on an ARM64 system,
a 64k runtime memory allocation is actually a 72k memory allocation as
tracked by the Page.c code because the guard pages are tracked as part
of the same allocation. This is a core function of the current heap
guard architecture.

This could also be fixed with rearchitecting the heap guard system to
respect alignment requirements and shift the guard pages inside of the
outer rounded allocation or by having guard pages be the runtime
granularity. Both of these approaches have issues. In the former case,
we break UEFI spec 2.10 section 2.3.6 for AARCH64, which states that
each 64k page for runtime memory regions may not have mixed memory
attributes, which pushing the guard pages inside would create. In the
latter case, an immense amount of memory is wasted to support such large
guard pages, and with pool guard many systems could not support an
additional 128k allocation for all runtime memory.

The simpler and safer solution is to disallow page and pool guards for
runtime memory allocations for systems that have a runtime granularity
greater than the EFI_PAGE_SIZE (4k). The usefulness of such guards is
limited, as OSes do not map guard pages today, so there is only boot
time protection of these ranges. This also prevents other bugs from
being exposed by using guards for regions that have a non-4k alignment
requirement, as again, multiple have cropped up because the heap guard
system was not built to support it.

This patch adds both a static assert to ensure that either the runtime
granularity is the EFI_PAGE_SIZE or that the PCD bits are not set to
enable heap guard for runtime memory regions. It also adds a check in
the page and pool allocation system to ensure that at runtime we are not
allocating a runtime region and attempt to guard it (the PCDs are close
to being removed in favor of dynamic heap guard configurations).

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4674
Github PR: https://github.com/tianocore/edk2/pull/5382

Cc: Leif Lindholm &lt;quic_llindhol@quicinc.com&gt;
Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;

Signed-off-by: Oliver Smith-Denny &lt;osde@linux.microsoft.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: Support customized FV Migration Information</title>
<updated>2023-12-25T04:57:18+00:00</updated>
<author>
<name>Cheng Sun</name>
<email>chengx.sun@intel.com</email>
</author>
<published>2023-12-21T02:45:22+00:00</published>
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<id>urn:sha1:1065536c64ab919ad5c207e50b82d4a88ac29ed8</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4533

There are use cases which not all FVs need be migrated from TempRam to
permanent memory before TempRam tears down. This new guid is introduced
to avoid unnecessary FV migration to improve boot performance. Platform
can publish MigrationInfo hob with this guid to customize FV migration
info, and PeiCore will only migrate FVs indicated by this Hob info.

This is a backwards compatible change, PeiCore will check MigrationInfo
hob before migration. If MigrationInfo hobs exists, only migrate FVs
recorded by hobs. If MigrationInfo hobs not exists, migrate all FVs to
permanent memory.

Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Guomin Jiang &lt;guomin.jiang@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Reviewed-by: Ray Ni &lt;ray.ni@intel.com&gt;
Signed-off-by: Cheng Sun &lt;chengx.sun@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: Add ImagePropertiesRecordLib</title>
<updated>2023-11-27T18:55:18+00:00</updated>
<author>
<name>Taylor Beebe</name>
<email>taylor.d.beebe@gmail.com</email>
</author>
<published>2023-11-03T15:29:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=8bc44608b8ea5807123bf2a050d15a66f0a4f4b0'/>
<id>urn:sha1:8bc44608b8ea5807123bf2a050d15a66f0a4f4b0</id>
<content type='text'>
Create a library for manipulating image properties records. The
library is currently blank and will be filled in a future patch
to help with reviewer readability.

Cc: Jian J Wang &lt;jian.j.wang@intel.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Dandan Bi &lt;dandan.bi@intel.com&gt;
Signed-off-by: Taylor Beebe &lt;taylor.d.beebe@gmail.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/DxeCore: Allow relocation of images with large address</title>
<updated>2023-10-31T14:40:50+00:00</updated>
<author>
<name>Jeff Brasen</name>
<email>jbrasen@nvidia.com</email>
</author>
<published>2023-05-15T23:48:56+00:00</published>
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<id>urn:sha1:aa8431822b7631659586247b1e50d21126f3cfcc</id>
<content type='text'>
Add PCD to control if modules with start addresses in PE/COFF &gt; 0x100000
attempt to load at specified address.
If a module has an address in this range and there is untested memory
DxeCore will attempt to promote all memory to tested which bypasses any
memory testing that would occur later in boot.

There are several existing AARCH64 option roms that have base addresses
of 0x180000000.

Signed-off-by: Jeff Brasen &lt;jbrasen@nvidia.com&gt;
Reviewed-by: Ashish Singhal &lt;ashishsingha@nvidia.com&gt;
Message-Id: &lt;bd36c9c24158590db2226ede05cb8c2f50c93a37.1684194452.git.jbrasen@nvidia.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
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