<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2.git/MdeModulePkg/Bus, branch trunk</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=trunk</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2.git/atom?h=trunk'/>
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<updated>2024-06-04T03:43:08+00:00</updated>
<entry>
<title>Renormalized end-of-lines from master@27b044605cd5f6b33a3d231576003850b3fe305b</title>
<updated>2024-06-04T03:43:08+00:00</updated>
<author>
<name>kx</name>
<email>kx@radix.pro</email>
</author>
<published>2024-06-04T03:43:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=7e2ccccace24636f29ddc210b94606abd4c7e42b'/>
<id>urn:sha1:7e2ccccace24636f29ddc210b94606abd4c7e42b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>MdeModulePkg: SpiHc: SpiHc Drivers</title>
<updated>2024-05-08T04:43:58+00:00</updated>
<author>
<name>Brit Chesley</name>
<email>brit.chesley@amd.com</email>
</author>
<published>2024-04-29T20:57:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=82b0358e3fd6be6d77e838618f69812bd28f26a2'/>
<id>urn:sha1:82b0358e3fd6be6d77e838618f69812bd28f26a2</id>
<content type='text'>
Added SpiHc DXE and SMM drivers. This code receives bus transactions
from the SpiBus layer and passes them onto the SpiHcPlatformLib

Platform Initialization Spec 1.7 volume 5 section 18.1.7

Bugzilla #4753

Cc: Abner Chang &lt;abner.chang@amd.com&gt;
Cc: Abdul Lateef Attar &lt;AbdulLateef.Attar@amd.com&gt;
Signed-off-by: Brit Chesley &lt;brit.chesley@amd.com&gt;
Reviewed-by: Abner Chang &lt;abner.chang@amd.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Bus/Spi/SpiBus: Adding SpiBus Drivers</title>
<updated>2024-05-08T04:43:58+00:00</updated>
<author>
<name>Brit Chesley</name>
<email>brit.chesley@amd.com</email>
</author>
<published>2024-04-29T20:32:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=efc7ccf9060e69a680dfa36111131a0951d983d3'/>
<id>urn:sha1:efc7ccf9060e69a680dfa36111131a0951d983d3</id>
<content type='text'>
Added SpiBus DXE and SMM drivers. This code translates SPI requests from
the application layer into SPI Bus transactions on the SPI host
controller. The code is responsible for checking if the transaction is
valid, then setting up the SPI clock and chip select properly before
passing the bus transaction to the host controller.

Platform Initialization Spec 1.7 volume 5 section 18.1.6

Bugzilla #4753

Cc: Abner Chang &lt;abner.chang@amd.com&gt;
Cc: Abdul Lateef Attar &lt;AbdulLateef.Attar@amd.com&gt;
Signed-off-by: Brit Chesley &lt;brit.chesley@amd.com&gt;
Reviewed-by: Abner Chang &lt;abner.chang@amd.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Add PCD for the delay of HCRST</title>
<updated>2024-05-07T04:48:09+00:00</updated>
<author>
<name>Xianglei Cai</name>
<email>xianglei.cai@intel.com</email>
</author>
<published>2024-05-07T01:15:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=1c0d4ae2c0fd24164873947c2e262c499ecf13b5'/>
<id>urn:sha1:1c0d4ae2c0fd24164873947c2e262c499ecf13b5</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=4727

Recently some of XHCI host controllers require to have
extra 1ms delay before accessing any MMIO register
during reset. PHY transition from P3 to P0 can take
around 1.3ms and the xHCI reset can take around 1.5ms.
Add PCD to control the delay, the default is 2 ms.

Cc: Ray Ni                   &lt;ray.ni@intel.com&gt;
Cc: Liming Gao               &lt;gaoliming@byosoft.com.cn&gt;
Cc: Krzysztof Lewandowski    &lt;krzysztof.lewandowski@intel.com&gt;
Cc: Jenny Huang              &lt;jenny.huang@intel.com&gt;
Cc: More Shih                &lt;more.shih@intel.com&gt;
Cc: Ian Chiu                 &lt;ian.chiu@intel.com&gt;
Signed-off-by: Xianglei Cai &lt;xianglei.cai@intel.com&gt;
Reviewed-by: Krzysztof Lewandowski &lt;krzysztof.lewandowski@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Reset endpoint while USB Transaction error</title>
<updated>2024-05-07T02:26:46+00:00</updated>
<author>
<name>Xianglei Cai</name>
<email>xianglei.cai@intel.com</email>
</author>
<published>2024-05-07T01:19:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=c12bbc14900aa5c70eec8c0576757c2182db3d01'/>
<id>urn:sha1:c12bbc14900aa5c70eec8c0576757c2182db3d01</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=4556

Based on XHCI spec 4.8.3, software should do the
reset endpoint while USB Transaction occur.
Add the error code for USB Transaction error
since UEFI spec don't have the related definition.

Cc: Ray Ni                  &lt;ray.ni@intel.com&gt;
Cc: Liming Gao              &lt;gaoliming@byosoft.com.cn&gt;
Cc: Krzysztof Lewandowski   &lt;krzysztof.lewandowski@intel.com&gt;
Cc: Jenny Huang             &lt;jenny.huang@intel.com&gt;
Cc: More Shih               &lt;more.shih@intel.com&gt;
Signed-off-by: Xianglei Cai &lt;xianglei.cai@intel.com&gt;
Reviewed-by: Krzysztof Lewandowski &lt;krzysztof.lewandowski@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/SpiNorFlashJedecSfdp: SPI NOR Flash JEDEC SFDP</title>
<updated>2024-04-20T08:26:40+00:00</updated>
<author>
<name>abnchang</name>
<email>abnchang@amd.com</email>
</author>
<published>2023-06-17T21:44:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=8b02ecc5f04cac5eb1b7c4a79a800e97bcf205fa'/>
<id>urn:sha1:8b02ecc5f04cac5eb1b7c4a79a800e97bcf205fa</id>
<content type='text'>
BZ#: 4471
SPI NOR Flash JEDEC Serial Flash Discoverable Driver
implementation.

Signed-off-by: Abner Chang &lt;abner.chang@amd.com&gt;
Cc: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Abdul Lateef Attar &lt;abdattar@amd.com&gt;
Cc: Brit Chesley &lt;brit.chesley@amd.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: Update the comments of ReadKeyStroke and ReadKeyStrokeEx</title>
<updated>2024-04-03T02:25:06+00:00</updated>
<author>
<name>Qingyu</name>
<email>qingyu.shang@intel.com</email>
</author>
<published>2024-03-11T08:18:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=e043e3e3bfec98de90386235c8d4c62b34e06665'/>
<id>urn:sha1:e043e3e3bfec98de90386235c8d4c62b34e06665</id>
<content type='text'>
Refer to Uefi spec 2.10 section 12.3.3, Add a new retval
EFI_UNSUPPORTED to EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.ReadKeyStrokeEx
and EFI_SIMPLE_TEXT_INPUT_PROTOCOL.ReadKeyStroke().

Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Qingyu &lt;qingyu.shang@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Xhci: Skip another size round up for TRB address</title>
<updated>2024-03-22T04:47:04+00:00</updated>
<author>
<name>Dat Mach</name>
<email>dmach@nvidia.com</email>
</author>
<published>2024-03-19T21:32:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=7f1ffba5de3d9840dbeeba20fba165f2fb724941'/>
<id>urn:sha1:7f1ffba5de3d9840dbeeba20fba165f2fb724941</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560

Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the DXE_ASSERT
caused by the TRB size round up from 16 to 64 for most cases.

However, there is a remaining case that the TRB size is also rounded up
during setting TR dequeue pointer that would trigger DXE_ASSERT.

This patch sets the alignment flag to FALSE in XhcSetTrDequeuePointer to
fix this issue as well.

Cc: Gao Cheng &lt;gao.cheng@intel.com&gt;
Cc: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;

Signed-off-by: Dat Mach &lt;dmach@nvidia.com&gt;
Reviewed-by: Gao Cheng &lt;gao.cheng@intel.com&gt;
Reviewed-by: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: Update ReceiveData and SendData function description</title>
<updated>2024-03-13T02:48:38+00:00</updated>
<author>
<name>Qingyu Shang</name>
<email>qingyu.shang@intel.com</email>
</author>
<published>2024-02-26T03:05:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=6f67ed45e03b554337daba2599a24b3352ad3438'/>
<id>urn:sha1:6f67ed45e03b554337daba2599a24b3352ad3438</id>
<content type='text'>
AtaBusDxe, NvmExpressDxe, ScsiDiskDxe and EmmcDxe is used to back the
EFI_STORAGE_SECURITY_COMMAND_PROTOCOL, update the parameter 'MediaId'
description for the protocol function ReceiveData and SendData as
described in UEFI Spec 2.10 section 13.14.

Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Qingyu Shang &lt;qingyu.shang@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Bus/Usb/UsbNetwork: Check array index range before access</title>
<updated>2024-02-26T20:46:12+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2024-02-15T19:16:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=1f161a7915e1c2c65bfaf7091712e9628107b707'/>
<id>urn:sha1:1f161a7915e1c2c65bfaf7091712e9628107b707</id>
<content type='text'>
Checks that an offset used to access array elements is within the
expected range before accessing the array item.

Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Rebecca Cran &lt;rebecca@bsdio.com&gt;
Cc: Richard Ho &lt;richardho@ami.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
</feed>
