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<title>Tianocore/edk2.git/MdeModulePkg/Bus/Pci, branch trunk</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=trunk</id>
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<updated>2024-06-04T03:43:08+00:00</updated>
<entry>
<title>Renormalized end-of-lines from master@27b044605cd5f6b33a3d231576003850b3fe305b</title>
<updated>2024-06-04T03:43:08+00:00</updated>
<author>
<name>kx</name>
<email>kx@radix.pro</email>
</author>
<published>2024-06-04T03:43:08+00:00</published>
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<id>urn:sha1:7e2ccccace24636f29ddc210b94606abd4c7e42b</id>
<content type='text'>
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</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Add PCD for the delay of HCRST</title>
<updated>2024-05-07T04:48:09+00:00</updated>
<author>
<name>Xianglei Cai</name>
<email>xianglei.cai@intel.com</email>
</author>
<published>2024-05-07T01:15:51+00:00</published>
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<id>urn:sha1:1c0d4ae2c0fd24164873947c2e262c499ecf13b5</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=4727

Recently some of XHCI host controllers require to have
extra 1ms delay before accessing any MMIO register
during reset. PHY transition from P3 to P0 can take
around 1.3ms and the xHCI reset can take around 1.5ms.
Add PCD to control the delay, the default is 2 ms.

Cc: Ray Ni                   &lt;ray.ni@intel.com&gt;
Cc: Liming Gao               &lt;gaoliming@byosoft.com.cn&gt;
Cc: Krzysztof Lewandowski    &lt;krzysztof.lewandowski@intel.com&gt;
Cc: Jenny Huang              &lt;jenny.huang@intel.com&gt;
Cc: More Shih                &lt;more.shih@intel.com&gt;
Cc: Ian Chiu                 &lt;ian.chiu@intel.com&gt;
Signed-off-by: Xianglei Cai &lt;xianglei.cai@intel.com&gt;
Reviewed-by: Krzysztof Lewandowski &lt;krzysztof.lewandowski@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Reset endpoint while USB Transaction error</title>
<updated>2024-05-07T02:26:46+00:00</updated>
<author>
<name>Xianglei Cai</name>
<email>xianglei.cai@intel.com</email>
</author>
<published>2024-05-07T01:19:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=c12bbc14900aa5c70eec8c0576757c2182db3d01'/>
<id>urn:sha1:c12bbc14900aa5c70eec8c0576757c2182db3d01</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=4556

Based on XHCI spec 4.8.3, software should do the
reset endpoint while USB Transaction occur.
Add the error code for USB Transaction error
since UEFI spec don't have the related definition.

Cc: Ray Ni                  &lt;ray.ni@intel.com&gt;
Cc: Liming Gao              &lt;gaoliming@byosoft.com.cn&gt;
Cc: Krzysztof Lewandowski   &lt;krzysztof.lewandowski@intel.com&gt;
Cc: Jenny Huang             &lt;jenny.huang@intel.com&gt;
Cc: More Shih               &lt;more.shih@intel.com&gt;
Signed-off-by: Xianglei Cai &lt;xianglei.cai@intel.com&gt;
Reviewed-by: Krzysztof Lewandowski &lt;krzysztof.lewandowski@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Xhci: Skip another size round up for TRB address</title>
<updated>2024-03-22T04:47:04+00:00</updated>
<author>
<name>Dat Mach</name>
<email>dmach@nvidia.com</email>
</author>
<published>2024-03-19T21:32:41+00:00</published>
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<id>urn:sha1:7f1ffba5de3d9840dbeeba20fba165f2fb724941</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560

Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the DXE_ASSERT
caused by the TRB size round up from 16 to 64 for most cases.

However, there is a remaining case that the TRB size is also rounded up
during setting TR dequeue pointer that would trigger DXE_ASSERT.

This patch sets the alignment flag to FALSE in XhcSetTrDequeuePointer to
fix this issue as well.

Cc: Gao Cheng &lt;gao.cheng@intel.com&gt;
Cc: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;

Signed-off-by: Dat Mach &lt;dmach@nvidia.com&gt;
Reviewed-by: Gao Cheng &lt;gao.cheng@intel.com&gt;
Reviewed-by: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg: Update ReceiveData and SendData function description</title>
<updated>2024-03-13T02:48:38+00:00</updated>
<author>
<name>Qingyu Shang</name>
<email>qingyu.shang@intel.com</email>
</author>
<published>2024-02-26T03:05:38+00:00</published>
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<id>urn:sha1:6f67ed45e03b554337daba2599a24b3352ad3438</id>
<content type='text'>
AtaBusDxe, NvmExpressDxe, ScsiDiskDxe and EmmcDxe is used to back the
EFI_STORAGE_SECURITY_COMMAND_PROTOCOL, update the parameter 'MediaId'
description for the protocol function ReceiveData and SendData as
described in UEFI Spec 2.10 section 13.14.

Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Qingyu Shang &lt;qingyu.shang@intel.com&gt;
Reviewed-by: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/PciBusDxe: Add feedback status for PciIoMap</title>
<updated>2024-01-25T09:45:03+00:00</updated>
<author>
<name>Sheng Wei</name>
<email>w.sheng@intel.com</email>
</author>
<published>2024-01-22T05:59:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=049695a0b1e2a9cbb7c2088a918f285bbb950999'/>
<id>urn:sha1:049695a0b1e2a9cbb7c2088a918f285bbb950999</id>
<content type='text'>
PciIoMap () need to feedback the status of
mIoMmuProtocol-&gt;SetAttribute () return value.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4652

Reviewed-by: Ray Ni &lt;ray.ni@intel.com&gt;
Reviewed-by: Huang Jenny &lt;jenny.huang@intel.com&gt;
Cc: Chiang Chris &lt;chris.chiang@intel.com&gt;
Signed-off-by: Sheng Wei &lt;w.sheng@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Bus: Fix XhciDxe Linker Issues</title>
<updated>2023-12-06T23:52:13+00:00</updated>
<author>
<name>Nate DeSimone</name>
<email>nathaniel.l.desimone@intel.com</email>
</author>
<published>2023-12-01T01:47:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=ff4c49a5ee38d613384fb2e318d891a800d32999'/>
<id>urn:sha1:ff4c49a5ee38d613384fb2e318d891a800d32999</id>
<content type='text'>
The DXE &amp; MM standalone variant of AcpiTimerLib defines a global
named mPerformanceCounterFrequency. A global with an identical
name is also present in MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c

Since XhciDxe has a dependency on TimerLib, this can cause link
errors due to the same symbol being defined twice if the platform
DSC chooses to use AcpiTimerLib as the TimerLib implementation for
any given platform.

To resolve this, I noted that some of the globals in Xhci.c are not
used outside of the Xhci.c compilation unit:

- mPerformanceCounterStartValue
- mPerformanceCounterEndValue
- mPerformanceCounterFrequency
- mPerformanceCounterValuesCached

I have changed the definition for all of these to static and added
an Xhci prefix. Since they are not used outside of the Xhci.c
compilation unit, there is no reason to have them exported as
globals.

Reviewed-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/Xhci: Skip size round up for TRB during address translation</title>
<updated>2023-09-28T02:02:11+00:00</updated>
<author>
<name>Gao Cheng</name>
<email>gao.cheng@intel.com</email>
</author>
<published>2023-09-13T06:16:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=f36e1ec1f0a5fd3be84913e09181d7813444b620'/>
<id>urn:sha1:f36e1ec1f0a5fd3be84913e09181d7813444b620</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560

TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI
device/host memory address, it may exceed xHCI host memory pool and
cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate
whether to enforce 64byte size alignment and round up. For TRB case,
should set it to FALSE to skip the size round up.

Signed-off-by: Gao Cheng &lt;gao.cheng@intel.com&gt;
Cc: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Jian J Wang &lt;jian.j.wang@intel.com&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Reviewed-by: Hao A Wu &lt;hao.a.wu@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Abort the Address Device cmd when time out</title>
<updated>2023-09-25T03:45:15+00:00</updated>
<author>
<name>Cai, Xianglei</name>
<email>xianglei.cai@intel.com</email>
</author>
<published>2023-09-21T03:57:40+00:00</published>
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<id>urn:sha1:d11f0ea045f598e08b414eeba4f8a74ac1b4ca0b</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=4552

Following XHCI spec 4.6.1.2, software may abort the
execution of Address Device Command when command failed
due to timeout.

Cc: Hao A Wu     &lt;hao.a.wu@intel.com&gt;
Cc: Ray Ni       &lt;ray.ni@intel.com&gt;
Cc: Jian J Wang  &lt;jian.j.wang@intel.com&gt;
Cc: Liming Gao   &lt;gaoliming@byosoft.com.cn&gt;
Cc: More Shih    &lt;more.shih@intel.com&gt;
Cc: Jenny Huang  &lt;jenny.huang@intel.com&gt;
Signed-off-by: Xianglei Cai &lt;xianglei.cai@intel.com&gt;
Reviewed-by: Hao A Wu &lt;hao.a.wu@intel.com&gt;
</content>
</entry>
<entry>
<title>MdeModulePkg/XhciDxe: Use Performance Timer for XHCI Timeouts</title>
<updated>2023-09-25T02:56:05+00:00</updated>
<author>
<name>Henz, Patrick</name>
<email>patrick.henz@hpe.com</email>
</author>
<published>2023-09-12T18:05:57+00:00</published>
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<id>urn:sha1:43dcf453fc15ca152945ca41dcce7f2f43a14313</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2948

XhciDxe uses the timer functionality provided by the
boot services table to detect timeout conditions. This
breaks the driver's ExitBootServices call back, as
CoreExitBootServices halts the timer before signaling
the ExitBootServices event. If the host controller
fails to halt in the call back, the timeout condition
will never occur and the boot gets stuck in an indefinite
spin loop. Use the free running timer provided by
TimerLib to calculate timeouts, avoiding the potential
hang.

Cc: Hao A Wu &lt;hao.a.wu@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Signed-off-by: Patrick Henz &lt;patrick.henz@hpe.com&gt;
Reviewed-by: Hao A Wu &lt;hao.a.wu@intel.com&gt;
</content>
</entry>
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