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<title>Tianocore/edk2.git/IntelFsp2WrapperPkg/Library, branch dependabot/github_actions/github/codeql-action-4</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Fgithub%2Fcodeql-action-4</id>
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<updated>2025-03-05T18:21:49+00:00</updated>
<entry>
<title>IntelFsp2WrapperPkg: Bootloader need to recover fs and gs</title>
<updated>2025-03-05T18:21:49+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2025-03-03T05:06:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=786ae7688414d58a14ef68b023af4b040f37323e'/>
<id>urn:sha1:786ae7688414d58a14ef68b023af4b040f37323e</id>
<content type='text'>
When enter FSP, bootloader need to save fs and gs, when back
to bootloader, bootloader need to restore fs and gs, so it
could avoid bootloader access wrong data segment when usging
fs and gs.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Save FspHobListPtr right after FspMemoryInit exits</title>
<updated>2024-12-25T02:56:26+00:00</updated>
<author>
<name>Du Lin</name>
<email>du.lin@intel.com</email>
</author>
<published>2024-12-20T15:49:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=da6504e5ccaa233b0ec051762809905f20ca5859'/>
<id>urn:sha1:da6504e5ccaa233b0ec051762809905f20ca5859</id>
<content type='text'>
Save FspHobList pointer to HOB right after FspMemoryInit exits so that
FspHobList pointer is available when performing platform related reset
in CallFspWrapperResetSystem(). Some platforms may consume FSP HOBs
prior to performing platform related reset.

Signed-off-by: Du Lin &lt;du.lin@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg/FspiWrapperPeim : Support API mode</title>
<updated>2024-12-20T06:29:58+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2024-10-07T13:15:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=df1726a65ef2f7f9793bbad4d18596ac7dbf0749'/>
<id>urn:sha1:df1726a65ef2f7f9793bbad4d18596ac7dbf0749</id>
<content type='text'>
Add fspsmm init interface for API mode.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Chen Gang C &lt;gang.c.chen@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Fsp T UPD Structure Bug Fix</title>
<updated>2024-04-09T17:15:10+00:00</updated>
<author>
<name>Duggapu Chinni B</name>
<email>chinni.b.duggapu@intel.com</email>
</author>
<published>2024-04-09T16:53:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=665789b61bc39de67d3f17288bacb4662434e251'/>
<id>urn:sha1:665789b61bc39de67d3f17288bacb4662434e251</id>
<content type='text'>
Add reserved bytes as per the latest spec.

Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ni Ray &lt;ray.ni@intel.com&gt;

Signed-off-by: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Reviewed-by: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Fsp T new ARCH UPD Support</title>
<updated>2024-04-09T17:15:10+00:00</updated>
<author>
<name>Duggapu Chinni B</name>
<email>chinni.b.duggapu@intel.com</email>
</author>
<published>2024-04-09T16:43:28+00:00</published>
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<id>urn:sha1:013006e4ef75ef6794a8e09c84f818ab5024da2f</id>
<content type='text'>
Changes in SecRamInitData to support spec changes

Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ni Ray &lt;ray.ni@intel.com&gt;

Signed-off-by: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Reviewed-by: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Error handling of TpmMeasureAndLogDataWithFlags()</title>
<updated>2024-03-15T09:05:25+00:00</updated>
<author>
<name>Du Lin</name>
<email>du.lin@intel.com</email>
</author>
<published>2024-03-12T02:30:06+00:00</published>
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<id>urn:sha1:ccbbc2a5c84a0330b28b726ef0936fc16937005a</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4700

TpmMeasureAndLogDataWithFlags() computes the measure the code and
log it into PCR 0. TpmMeasureAndLogData() computes the hash for the
configuration. The same "Status" variable is used to store the return
values for both of the functions. There is no error handling if
TpmMeasureAndLogDataWithFlags() returns an error Status.
Fix the issue by adding error handling for TpmMeasureAndLogDataWithFlags().

Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Chen Gang C &lt;gang.c.chen@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Susovan Mohapatra &lt;susovan.mohapatra@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Signed-off-by: Du Lin &lt;du.lin@intel.com&gt;
Reviewed-by: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Chen Gang C &lt;gang.c.chen@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Add variable initialization</title>
<updated>2023-11-09T12:31:33+00:00</updated>
<author>
<name>JasonX.Hsu</name>
<email>jasonx.hsu@intel.com</email>
</author>
<published>2023-11-09T06:18:12+00:00</published>
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<id>urn:sha1:616f0d503707c2e3fbdbc397ccb16a822f584b03</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4595

Fix build error when remove "-Wno-sometimes-uninitialized" option,
Add variable "FspMultiPhaseApiOffset" initialization.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Susovan Mohapatra &lt;susovan.mohapatra@intel.com&gt;
Cc: James Lu &lt;james.lu@intel.com&gt;
Reviewed-by: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Chen Gang C &lt;gang.c.chen@intel.com&gt;
Reviewed-by: Gua Guo &lt;gua.guo@intel.com&gt;
Signed-off-by: Jason Hsu &lt;jasonx.hsu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Check header revision for MultiPhase support.</title>
<updated>2022-10-25T23:12:10+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-10-25T18:43:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=26638d2aa399e436f47d629f877e581ed402020a'/>
<id>urn:sha1:26638d2aa399e436f47d629f877e581ed402020a</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4119

Earlier version of FSP header may not have MultiPhase fields present in
the FspInfoHeader so the handler should verify header revision before
accessing the MultiPhase fields from the header.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Add header for PlatformMultiPhaseLib.</title>
<updated>2022-10-05T04:13:53+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-10-04T20:10:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=f054beec548eb3cc718b35be20efa9d344fe7097'/>
<id>urn:sha1:f054beec548eb3cc718b35be20efa9d344fe7097</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4092

To comply with coding style rule each library class
should have its own header even if it is just a private child library
instance consumed by parent public library in the same package.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Fix code formatting errors</title>
<updated>2022-10-04T16:53:59+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2022-09-06T19:52:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=7c424c28b0adff2da455769521408dbf772c1ed7'/>
<id>urn:sha1:7c424c28b0adff2da455769521408dbf772c1ed7</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048

This package did not have CI enabled so code changes were merged
that fail uncrustify formatting. This change updates those files
to include uncustify formatting.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Michael D Kinney &lt;michael.d.kinney&gt;
</content>
</entry>
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