<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2.git/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c, branch master</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=master</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2.git/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/'/>
<updated>2024-04-09T17:15:10+00:00</updated>
<entry>
<title>IntelFsp2WrapperPkg: Fsp T UPD Structure Bug Fix</title>
<updated>2024-04-09T17:15:10+00:00</updated>
<author>
<name>Duggapu Chinni B</name>
<email>chinni.b.duggapu@intel.com</email>
</author>
<published>2024-04-09T16:53:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=665789b61bc39de67d3f17288bacb4662434e251'/>
<id>urn:sha1:665789b61bc39de67d3f17288bacb4662434e251</id>
<content type='text'>
Add reserved bytes as per the latest spec.

Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ni Ray &lt;ray.ni@intel.com&gt;

Signed-off-by: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Reviewed-by: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Fsp T new ARCH UPD Support</title>
<updated>2024-04-09T17:15:10+00:00</updated>
<author>
<name>Duggapu Chinni B</name>
<email>chinni.b.duggapu@intel.com</email>
</author>
<published>2024-04-09T16:43:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=013006e4ef75ef6794a8e09c84f818ab5024da2f'/>
<id>urn:sha1:013006e4ef75ef6794a8e09c84f818ab5024da2f</id>
<content type='text'>
Changes in SecRamInitData to support spec changes

Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ni Ray &lt;ray.ni@intel.com&gt;

Signed-off-by: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Reviewed-by: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Fix code formatting errors</title>
<updated>2022-10-04T16:53:59+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2022-09-06T19:52:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=7c424c28b0adff2da455769521408dbf772c1ed7'/>
<id>urn:sha1:7c424c28b0adff2da455769521408dbf772c1ed7</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048

This package did not have CI enabled so code changes were merged
that fail uncrustify formatting. This change updates those files
to include uncustify formatting.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Michael D Kinney &lt;michael.d.kinney&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64</title>
<updated>2022-04-16T00:18:14+00:00</updated>
<author>
<name>Ted Kuo</name>
<email>ted.kuo@intel.com</email>
</author>
<published>2022-04-15T08:37:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=91a03f78ba0b75bc4ed2c4b756cbe57c685d9c72'/>
<id>urn:sha1:91a03f78ba0b75bc4ed2c4b756cbe57c685d9c72</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added SecFspWrapperPlatformSecLibSample support for X64.
2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample.
3.Moved Fsp.h up one level to be shared across IA32 and X64.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Signed-off-by: Ted Kuo &lt;ted.kuo@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Apply uncrustify changes</title>
<updated>2021-12-07T17:24:28+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2021-12-05T22:54:00+00:00</published>
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<id>urn:sha1:7c7184e201a90a1d2376e615e55e3f4074731468</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the IntelFsp2WrapperPkg package

Cc: Andrew Fish &lt;afish@apple.com&gt;
Cc: Leif Lindholm &lt;leif@nuviainc.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Remove microcode related PCDs</title>
<updated>2021-05-31T03:14:08+00:00</updated>
<author>
<name>Lou, Yun</name>
<email>Yun.Lou@intel.com</email>
</author>
<published>2021-04-15T06:48:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=fe5da0927aad98f3c005088197fa30c1b8f9d3e8'/>
<id>urn:sha1:fe5da0927aad98f3c005088197fa30c1b8f9d3e8</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3334

IntelFsp2WrapperPkg defines following PCDs:
  PcdCpuMicrocodePatchAddress
  PcdCpuMicrocodePatchRegionSize
  PcdFlashMicrocodeOffset

But the PCD name caused confusion because UefiCpuPkg defines:
  PcdCpuMicrocodePatchAddress
  PcdCpuMicrocodePatchRegionSize

PcdCpuMicrocodePatchAddress in IntelFsp2WrapperPkg means the base
address of the FV that holds the microcode.
PcdCpuMicrocodePatchAddress in UefiCpuPkg means the address of the
microcode.

The relationship between the PCDs is:
IntelFsp2WrapperPkg.PcdCpuMicrocodePatchAddress
 +  IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset
 == UefiCpuPkg.PcdCpuMicrocodePatchAddress

IntelFsp2WrapperPkg.PcdCpuMicrocodePatchRegionSize
 -  IntelFsp2WrapperPkg.PcdFlashMicrocodeOffset
 == UefiCpuPkg.PcdCpuMicrocodePatchRegionSize

To avoid confusion and actually the PCDs in IntelFsp2WrapperPkg
are only used by a sample FSP-T wrapper, this patch removes
the 3 PCDs defined in IntelFsp2WrapperPkg.

The FSP-T wrapper is updated to directly use the ones in UefiCpuPkg.

Signed-off-by: Jason Lou &lt;yun.lou@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Add FSP*_ARCH_UPD.</title>
<updated>2020-06-23T04:22:49+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2020-06-18T12:59:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=1a992030522622c42aa063788b3276789c56c1e1'/>
<id>urn:sha1:1a992030522622c42aa063788b3276789c56c1e1</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781

Provides sample code to include FSPT_ARCH_UPD initial values with
UPD header revision set to 2.

Cc: Maurice Ma &lt;maurice.ma@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Replace BSD License with BSD+Patent License</title>
<updated>2019-04-09T17:58:03+00:00</updated>
<author>
<name>Michael D Kinney</name>
<email>michael.d.kinney@intel.com</email>
</author>
<published>2019-04-03T23:04:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=512e23a3339ddfb4d227d62feebe733825904de3'/>
<id>urn:sha1:512e23a3339ddfb4d227d62feebe733825904de3</id>
<content type='text'>
https://bugzilla.tianocore.org/show_bug.cgi?id=1373

Replace BSD 2-Clause License with BSD+Patent License.  This change is
based on the following emails:

  https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html
  https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html

RFCs with detailed process for the license change:

  V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html
  V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html
  V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>Add IntelFsp2Pkg and IntelFsp2WrapperPkg.</title>
<updated>2016-05-13T05:00:53+00:00</updated>
<author>
<name>Jiewen Yao</name>
<email>jiewen.yao@intel.com</email>
</author>
<published>2016-05-13T05:00:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=cf1d454983fb4fd3b580a92bd242310467a5eaef'/>
<id>urn:sha1:cf1d454983fb4fd3b580a92bd242310467a5eaef</id>
<content type='text'>
Add FSP2.0 support.
This series of patch is to support FSP2.0 specification at
https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf

Some major updates include:
1) One FSP binary is separated to multiple components:
FSP-T, FSP-M, FSP-S, and optional FSP-O.
Each component has its own configuration data region.
2) All FSP-APIs use same UPD format - FSP_UPD_HEADER.
3) Add EnumInitPhaseEndOfFirmware notifyphase.
4) FSP1.1/FSP1.0 compatibility is NOT maintained.
5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg,
to indicate that it is for FspWrapper only.

IntelFspPkg and IntelFspWrapperPkg will be deprecated.
The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg
and IntelFsp2WrapperPkg.
The old platform can still use IntelFspPkg and IntelFspWrapperPkg
for compatibility consideration.

Cc: Giri P Mudusuru &lt;giri.p.mudusuru@intel.com&gt;
Cc: Maurice Ma &lt;maurice.ma@intel.com&gt;
Cc: Ravi P Rangarajan &lt;ravi.p.rangarajan@intel.com&gt;
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao &lt;jiewen.yao@intel.com&gt;
Reviewed-by: Giri P Mudusuru &lt;giri.p.mudusuru@intel.com&gt;
Reviewed-by: Maurice Ma &lt;maurice.ma@intel.com&gt;
Reviewed-by: Ravi P Rangarajan &lt;ravi.p.rangarajan@intel.com&gt;
</content>
</entry>
</feed>
