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<title>Tianocore/edk2.git/IntelFsp2WrapperPkg/FspsWrapperPeim, branch dependabot/github_actions/github/codeql-action-4</title>
<subtitle>EDK II (mirror)</subtitle>
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<updated>2025-10-30T08:13:29+00:00</updated>
<entry>
<title>IntelFsp2WrapperPkg: Rebase FSP-S and FSP-I if Image Base not match</title>
<updated>2025-10-30T08:13:29+00:00</updated>
<author>
<name>Zhiguang Liu</name>
<email>zhiguang.liu@intel.com</email>
</author>
<published>2025-09-25T08:45:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=426da7fb1a2d9155d2abf3a68b93ff37ed6898b1'/>
<id>urn:sha1:426da7fb1a2d9155d2abf3a68b93ff37ed6898b1</id>
<content type='text'>
FSP Spec says: "The FSP is not Position Independent Code (PIC) and
each FSP component has to be rebased if it is placed at a location
which is different from the preferred base address specified during
the FSP build."
Normally, the FSP location in flash is the same preferred base
address specified during the FSP build. To avoid FSP-S and FSP-I
running directly from flash, platform may copy the FSP binaries into
physical memory. This causes FSP location to be different from the
preferred base address.
To support this, this commit checks the Image Base from FSP header
and the FSP base address PCD. If these two are different, This commit
assumes the FSP is copied into physical memory and FSP location is
changed. In such scenario, the commit will rebase the FSP to the address
provided by the PCD.

Signed-off-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Prevent null pointer dereference</title>
<updated>2024-10-28T16:10:09+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2024-09-27T20:46:07+00:00</published>
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<id>urn:sha1:4de80843a74475aef3ac47127cec0e52c1f5aa46</id>
<content type='text'>
Return from `FspsWrapperInitDispatchMode()` if a buffer allocation
fails instead of attempting to dereference the pointer.

Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Get HobListPtr before calling the Multiphase FSPS</title>
<updated>2023-06-26T05:09:24+00:00</updated>
<author>
<name>Aishwarya, KurugoduMelmatamX</name>
<email>kurugodumelmatamx.aishwarya@intel.com</email>
</author>
<published>2023-06-12T05:24:15+00:00</published>
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<id>urn:sha1:ac33eee8b83999ba591af04fe22e773cf8fc8193</id>
<content type='text'>
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4480

In the FspsWrapperPeim, before calling FspWrapperVariableRequestHandler
and FspWrapperMultiPhaseHandler ,FspHobListPtr should be available so
that BL will be able to get the correct FspHobListPtr value

Signed-off-by: kurugodx &lt;kurugodumelmatamx.aishwarya@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Chen Gang C &lt;gang.c.chen@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Susovan Mohapatra &lt;susovan.mohapatra@intel.com&gt;
Reviewed-by: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Fix ASSERT when FSP-S/M use FFS3.</title>
<updated>2023-05-30T03:56:58+00:00</updated>
<author>
<name>Tan, Ming</name>
<email>ming.tan@intel.com</email>
</author>
<published>2023-05-22T06:13:06+00:00</published>
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<id>urn:sha1:69e10f02111bf7e719237f05233abff4e50016fa</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4458

Original code call PeiServicesInstallFvInfoPpi() with NULL for the
FvFormat parameter, then PeiServicesInstallFvInfoPpi() will assume it
use FFS2, then ASSERT if FSP-S/M use FFS3.
Now set the FvFormat to the info got from FvHeader.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Signed-off-by: Ming Tan &lt;ming.tan@intel.com&gt;
Reviewed-by: S Ashraf Ali &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Remove UefiCpuLib from module INFs.</title>
<updated>2023-03-10T08:23:56+00:00</updated>
<author>
<name>Yu Pu</name>
<email>yu.pu@intel.com</email>
</author>
<published>2022-03-29T03:45:12+00:00</published>
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<id>urn:sha1:fa78edc57eb000f7820d5896f61053069b61eba1</id>
<content type='text'>
Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the
dependency of UefiCpuLib.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Yu Pu &lt;yu.pu@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers.</title>
<updated>2022-09-26T20:22:44+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-08-10T00:35:50+00:00</published>
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<id>urn:sha1:96f3efbd991db83c608909c1c861a77fe26982f1</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Implement MultiPhase wrapper handlers and only call to MultiPhase
handlers when FSP supports.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Support 64bit FspResetType for X64 build.</title>
<updated>2022-07-19T22:24:31+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-07-19T04:08:31+00:00</published>
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<id>urn:sha1:24eac4caf31afae48349af44588a52783c1819b8</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999
FspResetType will be either 32bit or 64 bit basing on
the build type.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg: Add CpuLib to module INFs that depend on UefiCpuLib.</title>
<updated>2022-05-06T07:48:15+00:00</updated>
<author>
<name>Yu Pu</name>
<email>yu.pu@intel.com</email>
</author>
<published>2022-03-28T15:05:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=3afa0a20966dee37406175fa7ddd04010ecc85d1'/>
<id>urn:sha1:3afa0a20966dee37406175fa7ddd04010ecc85d1</id>
<content type='text'>
There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and
UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build
failure, add CpuLib dependency to all modules that depend on UefiCpuLib.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Yu Pu &lt;yu.pu@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg : Remove EFIAPI from local functions.</title>
<updated>2021-12-22T05:11:50+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2021-12-21T00:33:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=9ec2cc1f3138ef9314314df29fc6ce0aa5e120b9'/>
<id>urn:sha1:9ec2cc1f3138ef9314314df29fc6ce0aa5e120b9</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642

Local functions do not need EFIAPI.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Star Zeng &lt;star.zeng@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type</title>
<updated>2021-12-20T03:42:50+00:00</updated>
<author>
<name>S, Ashraf Ali</name>
<email>ashraf.ali.s@intel.com</email>
</author>
<published>2021-12-16T08:10:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=de9e5b7dc721d4ca319c0455cf83577347e0abef'/>
<id>urn:sha1:de9e5b7dc721d4ca319c0455cf83577347e0abef</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to building
error. when a module built-in X64 function pointer will be the size of
64bit width which cannot be fit in 32bit address which will lead to
error. to overcome this issue introducing the 2 new PCD's for the 64bit
modules can consume it. based on the which pcd platform set, use that.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Kuo Ted &lt;ted.kuo@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Rangasai V Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Digant H Solanki &lt;digant.h.solanki@intel.com&gt;
Cc: Sangeetha V &lt;sangeetha.v@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Signed-off-by: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Star Zeng &lt;star.zeng@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
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