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<title>Tianocore/edk2.git/IntelFsp2Pkg, branch dependabot/github_actions/actions/setup-python-7</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-7</id>
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<updated>2026-04-09T20:12:55+00:00</updated>
<entry>
<title>IntelFsp2Pkg/FspSecCore/Vtf0: NASM and Python 3 fixes</title>
<updated>2026-04-09T20:12:55+00:00</updated>
<author>
<name>Michael D Kinney</name>
<email>michael.d.kinney@intel.com</email>
</author>
<published>2026-03-27T23:48:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=11a89ec0305fe816330a0ae61978cdf7be88eb53'/>
<id>urn:sha1:11a89ec0305fe816330a0ae61978cdf7be88eb53</id>
<content type='text'>
Update NASM files to use NASM file extensions.

Also update VTF0 Python scripts to Python 3.

Signed-off-by: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/FspSecCore: Do not hang when bootloader IDT is larger</title>
<updated>2026-03-19T05:40:01+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-03-18T05:07:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=ff2543960090c9c74c679d368a9051bbcd6424e0'/>
<id>urn:sha1:ff2543960090c9c74c679d368a9051bbcd6424e0</id>
<content type='text'>
The current logic in FspSecCore is when the size of IDT created
by the bootloader is larger than the size of IDT that's going to be created
by FSP, CpuDeadLoop() is hit.

Change PcdFspMaxInterruptSupported from 34 to 255 to avoid such case.

Even when the PCD is overriden to a small value, the dead-loop is
not necessary. The patch updates the logic to only copy
the first part of the IDT entries when bootloader's IDT is larger.
A warn is printed in the debug log when such case happens.

The change addresses a boot hang in FSP API mode introduced by
commit 3454d7ab41.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/FspSecCore: Allocate correct number of IDT entries on stack</title>
<updated>2026-03-19T05:40:01+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-03-18T05:02:40+00:00</published>
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<id>urn:sha1:819af4cd11f4fe095a0cf149c6aa36b6917434bb</id>
<content type='text'>
PcdFspMaxInterruptSupported is the max interrupt number but it is used as
number of interrupts when defining SEC_IDT_TABLE.

Fix it by changing the SEC_IDT_TABLE.IdtTable array from
  IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];
to
  IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported) + 1];

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Save/restore FSBASE/GSBASE in entry and exit</title>
<updated>2026-03-09T16:21:26+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-02-27T06:03:06+00:00</published>
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<id>urn:sha1:11868992cc297387878bd9fb69db3c7aaa094f31</id>
<content type='text'>
FSP may store something in FSBASE/GSBASE while bootloader may do so as well.
Add the FSBASE/GSBASE save/restore logic in the FSP entry and exit
to avoid the contents in FSBASE/GSBASE are corrupted by the other party.

The change assumes there is no very old CPU that does not support
rdfsbase/wrfsbase/rdgsbase/wrgsbase instructions.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Remove GCC48/49/5 build options from QemuFspPkg.dsc</title>
<updated>2026-02-26T15:30:52+00:00</updated>
<author>
<name>Mike Beaton</name>
<email>mjsbeaton@gmail.com</email>
</author>
<published>2026-01-24T17:03:31+00:00</published>
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<id>urn:sha1:6900f80295e46e393464b3f507a9b4a734aacc91</id>
<content type='text'>
no-pic no-pie were already specified in GCC and GCC5, so it is believed
the removed GCC5 options were no longer necessary before this change,
and do not need to be transferred to GCC5.

Signed-off-by: Mike Beaton &lt;mjsbeaton@gmail.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/PatchFv: Fix _IMAGE_BASE_&lt;module&gt;_ not exist with CLANG</title>
<updated>2026-02-24T06:00:16+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-02-13T03:44:59+00:00</published>
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<id>urn:sha1:c8062ec623d90f7a6740156f7020a7f7b5ee6be8</id>
<content type='text'>
Commit 677baf5b4a adds a pseudo symbol _IMAGE_BASE_&lt;module&gt;_ for image base.
But it contains a bug that when CLANG toolchain is used the pseudo symbol
does not exist.
The patch fixes the issue.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Replace include guards with #pragma once</title>
<updated>2026-02-23T21:01:28+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2026-02-03T18:35:59+00:00</published>
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<id>urn:sha1:86047d47423134a74cad7da53c8dbc06fccb0f20</id>
<content type='text'>
Replace traditional `#ifndef`/`#define`/`#endif` include guards with
`#pragma` once.

`#pragma once` is a widely supported preprocessor directive that
prevents header files from being included multiple times. It is
supported by all toolchains used to build edk2: GCC, Clang/LLVM, and
MSVC.

Compared to macro-based include guards, `#pragma once`:

- Eliminates the risk of macro name collisions or copy/paste errors
  where two headers inadvertently use the same guard macro.
- Eliminate inconsistency in the way include guard macros are named
  (e.g., some files use `__FILE_H__`, others use `FILE_H_`, etc.).
- Reduces boilerplate (three lines replaced by one).
- Avoids polluting the macro namespace with guard symbols.
- Can improve build times as the preprocessor can skip re-opening the
  file entirely, rather than re-reading it to find the matching
  `#endif` ("multiple-include optimization").
  - Note that some compilers may already optimize traditional include
    guards, by recognzining the idiomatic pattern.

This change is made acknowledging that overall portability of the
code will technically be reduced, as `#pragma once` is not part of the
C/C++ standards.

However, this is considered acceptable given:

1. edk2 already defines a subset of supported compilers in
   BaseTools/Conf/tools_def.template, all of which have supported
   `#pragma once` for over two decades.
2. There have been concerns raised to the project about inconsistent
   include guard naming and potential macro collisions.

Approximate compiler support dates:

- MSVC: Supported since Visual C++ 4.2 (1996)
- GCC: Supported since 3.4 (2004)
  (http://gnu.ist.utl.pt/software/gcc/gcc-3.4/changes.html)
- Clang (LLVM based): Since initial release in 2007

Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/PatchFv.py: Support pseudo symbol for image base</title>
<updated>2026-01-21T06:54:22+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-01-19T09:19:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=c666d125b09c8abfa8e8b2ee09c6d89e9f4132e9'/>
<id>urn:sha1:c666d125b09c8abfa8e8b2ee09c6d89e9f4132e9</id>
<content type='text'>
Define a pseudo symbol _IMAGE_BASE_&lt;moduleName&gt;_ for returnning
the PE/TE image base address.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Migrate GDT in SecTemporaryRamSupport</title>
<updated>2025-11-23T02:42:34+00:00</updated>
<author>
<name>Zhiguang Liu</name>
<email>zhiguang.liu@intel.com</email>
</author>
<published>2025-11-03T03:54:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=f12137456ab40ecfcf99ed93126fb3fbd78afb45'/>
<id>urn:sha1:f12137456ab40ecfcf99ed93126fb3fbd78afb45</id>
<content type='text'>
FSP API mode is using a separate GDT, which may be in NEM or flash.
Need to migrate it into permanent memory

Signed-off-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Correct ApiIdx type</title>
<updated>2025-11-23T01:55:17+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2025-11-05T05:20:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=2fda942498a6de86ca69a7c9f26eeef99bf55dc3'/>
<id>urn:sha1:2fda942498a6de86ca69a7c9f26eeef99bf55dc3</id>
<content type='text'>
For function FspMultiPhasePlatformGetNumberOfPhases, the type
of ApiIdx is not aligned in header file and c function, correct
and make it align.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
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