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<title>Tianocore/edk2.git/IntelFsp2Pkg/Library, branch dependabot/github_actions/actions/setup-python-7</title>
<subtitle>EDK II (mirror)</subtitle>
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<updated>2026-03-09T16:21:26+00:00</updated>
<entry>
<title>IntelFsp2Pkg: Save/restore FSBASE/GSBASE in entry and exit</title>
<updated>2026-03-09T16:21:26+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-02-27T06:03:06+00:00</published>
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<id>urn:sha1:11868992cc297387878bd9fb69db3c7aaa094f31</id>
<content type='text'>
FSP may store something in FSBASE/GSBASE while bootloader may do so as well.
Add the FSBASE/GSBASE save/restore logic in the FSP entry and exit
to avoid the contents in FSBASE/GSBASE are corrupted by the other party.

The change assumes there is no very old CPU that does not support
rdfsbase/wrfsbase/rdgsbase/wrgsbase instructions.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Replace include guards with #pragma once</title>
<updated>2026-02-23T21:01:28+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2026-02-03T18:35:59+00:00</published>
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<id>urn:sha1:86047d47423134a74cad7da53c8dbc06fccb0f20</id>
<content type='text'>
Replace traditional `#ifndef`/`#define`/`#endif` include guards with
`#pragma` once.

`#pragma once` is a widely supported preprocessor directive that
prevents header files from being included multiple times. It is
supported by all toolchains used to build edk2: GCC, Clang/LLVM, and
MSVC.

Compared to macro-based include guards, `#pragma once`:

- Eliminates the risk of macro name collisions or copy/paste errors
  where two headers inadvertently use the same guard macro.
- Eliminate inconsistency in the way include guard macros are named
  (e.g., some files use `__FILE_H__`, others use `FILE_H_`, etc.).
- Reduces boilerplate (three lines replaced by one).
- Avoids polluting the macro namespace with guard symbols.
- Can improve build times as the preprocessor can skip re-opening the
  file entirely, rather than re-reading it to find the matching
  `#endif` ("multiple-include optimization").
  - Note that some compilers may already optimize traditional include
    guards, by recognzining the idiomatic pattern.

This change is made acknowledging that overall portability of the
code will technically be reduced, as `#pragma once` is not part of the
C/C++ standards.

However, this is considered acceptable given:

1. edk2 already defines a subset of supported compilers in
   BaseTools/Conf/tools_def.template, all of which have supported
   `#pragma once` for over two decades.
2. There have been concerns raised to the project about inconsistent
   include guard naming and potential macro collisions.

Approximate compiler support dates:

- MSVC: Supported since Visual C++ 4.2 (1996)
- GCC: Supported since 3.4 (2004)
  (http://gnu.ist.utl.pt/software/gcc/gcc-3.4/changes.html)
- Clang (LLVM based): Since initial release in 2007

Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Correct ApiIdx type</title>
<updated>2025-11-23T01:55:17+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2025-11-05T05:20:48+00:00</published>
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<id>urn:sha1:2fda942498a6de86ca69a7c9f26eeef99bf55dc3</id>
<content type='text'>
For function FspMultiPhasePlatformGetNumberOfPhases, the type
of ApiIdx is not aligned in header file and c function, correct
and make it align.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Preserve GDTR and CS/DS/ES/FS/GS/SS</title>
<updated>2025-07-18T06:21:48+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-15T07:41:50+00:00</published>
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<id>urn:sha1:562bce0febd641f78df7cd61f2ed5a4c944b31ac</id>
<content type='text'>
Bootloader does not expect FSP modifies GDTR and segment selectors, update
FSP entry/exit code to preserve these registers.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/FspMultiPhaseLib: Remove EFIAPI for local function</title>
<updated>2025-07-16T06:47:27+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-15T07:43:07+00:00</published>
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<id>urn:sha1:83794b8e968e0928aec5333b66d094d0ae289770</id>
<content type='text'>
FspMultiPhaseWorker() is a local function that's called from
FspMultiPhaseMemInitApiHandler()
and FspMultiPhaseSiInitApiHandlerV2().

Remove "EFIAPI" from its function header.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/FspCommonLib: Remove unused API SetFspCoreStackPointer()</title>
<updated>2025-07-16T06:47:27+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-14T07:48:15+00:00</published>
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<id>urn:sha1:36b63e9fc87e4494067fb2cfa702449cfbb55b86</id>
<content type='text'>
Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/CacheLib: Make integer width consistent in loop condition</title>
<updated>2025-05-24T01:06:53+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2025-04-30T15:28:32+00:00</published>
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<id>urn:sha1:ee6a2bfc2c9cfadc05ca0ecaaf17734521bb7aa0</id>
<content type='text'>
Explicitly casts `mFixedMtrrTable[MsrNum].Length` to resolve a
`comparison-with-wider-type` CodeQL error.

https://codeql.github.com/codeql-query-help/cpp/cpp-comparison-with-wider-type/

Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg : Refactor BaseFspCommonLib to reduce binary size</title>
<updated>2024-09-30T08:15:35+00:00</updated>
<author>
<name>Ashraf Ali</name>
<email>ashraf.ali.s@intel.com</email>
</author>
<published>2024-09-08T15:15:00+00:00</published>
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<id>urn:sha1:a6b472131e6f49ec6ec309a06fed3b70b97a8602</id>
<content type='text'>
Moved FspApiReturnStatusReset API to a separate file to eliminate
unnecessary inclusion of FspApiReturnStatusReset APIs in driver binary.

When the compiler linking the Object files it may not remove all the
unused from NASM OBJs. This change is to reorganize the C files to
minimize the impact of the NASM behavior resulting is code size
reduction.

Signed-off-by: Ashraf Ali &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Support FSP API to save and restore page table</title>
<updated>2024-09-11T05:45:54+00:00</updated>
<author>
<name>Zhiguang Liu</name>
<email>zhiguang.liu@intel.com</email>
</author>
<published>2024-06-18T08:13:12+00:00</published>
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<id>urn:sha1:14c9ba1a2ca64137de148968823dc20988dcaa4c</id>
<content type='text'>
A potential issue may happen when FSP creates/changes page table while
bootloader doesn't expect page table being changed in FSP.
Current, FSP API support to save/restore stack, IDT and general purpose
registers. Following the same pattern, add save/restore page table
support to solve this issue.
Note that this feature only impacts FSP API mode, and is controlled
by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD
default value is set as FALSE.

Signed-off-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Align FSP global data pointer for X64 build</title>
<updated>2024-08-28T13:40:56+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2024-07-26T02:16:42+00:00</published>
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<id>urn:sha1:1fd2f9ec8f16cc8efb949888db94eb42006f77c6</id>
<content type='text'>
When it used 32 bits for set FSP global data pointer under X64 build,
it should get FSP global data pointer with 32 bits data under X64 build.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
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