<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2.git/IntelFsp2Pkg/Library/BaseFspSwitchStackLib, branch dependabot/github_actions/actions/setup-python-7</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-7</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-7'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/'/>
<updated>2026-03-09T16:21:26+00:00</updated>
<entry>
<title>IntelFsp2Pkg: Save/restore FSBASE/GSBASE in entry and exit</title>
<updated>2026-03-09T16:21:26+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-02-27T06:03:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=11868992cc297387878bd9fb69db3c7aaa094f31'/>
<id>urn:sha1:11868992cc297387878bd9fb69db3c7aaa094f31</id>
<content type='text'>
FSP may store something in FSBASE/GSBASE while bootloader may do so as well.
Add the FSBASE/GSBASE save/restore logic in the FSP entry and exit
to avoid the contents in FSBASE/GSBASE are corrupted by the other party.

The change assumes there is no very old CPU that does not support
rdfsbase/wrfsbase/rdgsbase/wrgsbase instructions.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Preserve GDTR and CS/DS/ES/FS/GS/SS</title>
<updated>2025-07-18T06:21:48+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-15T07:41:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=562bce0febd641f78df7cd61f2ed5a4c944b31ac'/>
<id>urn:sha1:562bce0febd641f78df7cd61f2ed5a4c944b31ac</id>
<content type='text'>
Bootloader does not expect FSP modifies GDTR and segment selectors, update
FSP entry/exit code to preserve these registers.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Support FSP API to save and restore page table</title>
<updated>2024-09-11T05:45:54+00:00</updated>
<author>
<name>Zhiguang Liu</name>
<email>zhiguang.liu@intel.com</email>
</author>
<published>2024-06-18T08:13:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=14c9ba1a2ca64137de148968823dc20988dcaa4c'/>
<id>urn:sha1:14c9ba1a2ca64137de148968823dc20988dcaa4c</id>
<content type='text'>
A potential issue may happen when FSP creates/changes page table while
bootloader doesn't expect page table being changed in FSP.
Current, FSP API support to save/restore stack, IDT and general purpose
registers. Following the same pattern, add save/restore page table
support to solve this issue.
Note that this feature only impacts FSP API mode, and is controlled
by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD
default value is set as FALSE.

Signed-off-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/SwitchStack: Reserve 32B when calling C function in 64bit</title>
<updated>2023-11-03T19:41:25+00:00</updated>
<author>
<name>Ni, Ray</name>
<email>ray.ni@intel.com</email>
</author>
<published>2023-10-31T08:22:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=0b4acb88d67520ad5cd9fd8896db0a2e203eaca4'/>
<id>urn:sha1:0b4acb88d67520ad5cd9fd8896db0a2e203eaca4</id>
<content type='text'>
When FSP runs in API mode, it saves the IDTR in its own stack then
switches to bootloader's stack before it returns from FspMemoryInit.
Next time when the bootloader calls TempRamExit, FSP switches to
its own stack and restores IDTR from its stack saved earlier.

However, due to a bug in BaseFspSwitchStackLib, the IDTR saved on
FSP's stack might be corrupted that results the following TempRamExit
call fails inside FSP due to PeiServices pointer cannot be retrieved
from IDT.base - 8.

The bug is the assembly code doesn't reserve 32 bytes before calling
the C routine in 64bit. According to the x86-64 calling convention,
caller is responsible for allocating 32 bytes of "shadow space" on the
stack right before calling the function (regardless of the actual
number of parameters used).

When FSP is built in optimization-off mode, the C routine makes use
of the 32-byte "shadow space" which is not reserved by the assembly
caller. That causes the IDTR saved on the stack is corrupted by the
C routine.
The patch fixes so by reserving the 32 bytes before calling C routine.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ray Han Lim Ng &lt;ray.han.lim.ng@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Reviewed-by: Ted Kuo &lt;ted.kuo@intel.com&gt;
Reviewed-by: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Susovan Mohapatra &lt;susovan.mohapatra@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Fix code formatting errors</title>
<updated>2022-10-04T16:53:59+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2022-09-06T17:45:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=629709a51d76fe6ad22a5441fb979a1b8c9d2e16'/>
<id>urn:sha1:629709a51d76fe6ad22a5441fb979a1b8c9d2e16</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048

This package did not have CI enabled so code changes were merged
that fail uncrustify formatting. This change updates those files
to include uncustify formatting.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Michael D Kinney &lt;michael.d.kinney&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: FspSecCore support for X64</title>
<updated>2022-04-16T00:18:14+00:00</updated>
<author>
<name>Ted Kuo</name>
<email>ted.kuo@intel.com</email>
</author>
<published>2022-04-15T08:37:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=00aa71ce20472f0a7bc01e735a0c419adf727def'/>
<id>urn:sha1:00aa71ce20472f0a7bc01e735a0c419adf727def</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FspSecCore support for X64.
2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported.
3.Corrected few typos.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Signed-off-by: Ted Kuo &lt;ted.kuo@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit</title>
<updated>2022-04-16T00:18:14+00:00</updated>
<author>
<name>Ted Kuo</name>
<email>ted.kuo@intel.com</email>
</author>
<published>2022-04-15T08:37:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=630df8c86eac64f918aa74f52cbf042db033d3db'/>
<id>urn:sha1:630df8c86eac64f918aa74f52cbf042db033d3db</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added EFIAPI to FspNotifyPhasePeimEntryPoint, SwapStack and
  PEI_CORE_ENTRY.
2.Treat both MAX_ADDRESS and MAX_UINT32 as invalid address for
  FSP global data in FspApiCallingCheck().
3.Changed AsmReadEsp to AsmReadStackPointer.
4.Changed the type of the return value of AsmReadStackPointer
  from UINT32 to UINTN.
5.Changed the type of TemporaryMemoryBase, PermenentMemoryBase
  and BootLoaderStack from UINT32 to UINTN.
6.Some type casting to pointers are UINT32. Changed them to
  UINTN to accommodate both IA32 and X64.
7.Corrected some typos.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Signed-off-by: Ted Kuo &lt;ted.kuo@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: BaseFspSwitchStackLib Support for X64</title>
<updated>2022-03-17T13:23:28+00:00</updated>
<author>
<name>Kuo, Ted</name>
<email>ted.kuo@intel.com</email>
</author>
<published>2022-03-14T02:48:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=411b3ff6ddb4042374a6e61285dac9f5a227f652'/>
<id>urn:sha1:411b3ff6ddb4042374a6e61285dac9f5a227f652</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3832
Add BaseFspSwitchStackLib Support for X64.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Signed-off-by: Ted Kuo &lt;ted.kuo@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Apply uncrustify changes</title>
<updated>2021-12-07T17:24:28+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2021-12-05T22:53:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=111f2228ddf487b0ac3491e416bb3dcdcfa4f979'/>
<id>urn:sha1:111f2228ddf487b0ac3491e416bb3dcdcfa4f979</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the IntelFsp2Pkg package

Cc: Andrew Fish &lt;afish@apple.com&gt;
Cc: Leif Lindholm &lt;leif@nuviainc.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Fix various typos</title>
<updated>2019-07-11T13:07:17+00:00</updated>
<author>
<name>Antoine Cœur</name>
<email>coeur@gmx.fr</email>
</author>
<published>2019-07-11T08:54:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=91cc60bafc7d6e49b7bc85990f895d6228f51364'/>
<id>urn:sha1:91cc60bafc7d6e49b7bc85990f895d6228f51364</id>
<content type='text'>
Fix various typos in IntelFsp2Pkg.

Signed-off-by: Cœur &lt;coeur@gmx.fr&gt;
Reviewed-by: Star Zeng &lt;star.zeng@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
</feed>
