<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2.git/IntelFsp2Pkg/Library/BaseFspCommonLib, branch dependabot/github_actions/actions/setup-python-7</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-7</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-7'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/'/>
<updated>2026-03-09T16:21:26+00:00</updated>
<entry>
<title>IntelFsp2Pkg: Save/restore FSBASE/GSBASE in entry and exit</title>
<updated>2026-03-09T16:21:26+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2026-02-27T06:03:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=11868992cc297387878bd9fb69db3c7aaa094f31'/>
<id>urn:sha1:11868992cc297387878bd9fb69db3c7aaa094f31</id>
<content type='text'>
FSP may store something in FSBASE/GSBASE while bootloader may do so as well.
Add the FSBASE/GSBASE save/restore logic in the FSP entry and exit
to avoid the contents in FSBASE/GSBASE are corrupted by the other party.

The change assumes there is no very old CPU that does not support
rdfsbase/wrfsbase/rdgsbase/wrgsbase instructions.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Preserve GDTR and CS/DS/ES/FS/GS/SS</title>
<updated>2025-07-18T06:21:48+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-15T07:41:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=562bce0febd641f78df7cd61f2ed5a4c944b31ac'/>
<id>urn:sha1:562bce0febd641f78df7cd61f2ed5a4c944b31ac</id>
<content type='text'>
Bootloader does not expect FSP modifies GDTR and segment selectors, update
FSP entry/exit code to preserve these registers.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/FspCommonLib: Remove unused API SetFspCoreStackPointer()</title>
<updated>2025-07-16T06:47:27+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-14T07:48:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=36b63e9fc87e4494067fb2cfa702449cfbb55b86'/>
<id>urn:sha1:36b63e9fc87e4494067fb2cfa702449cfbb55b86</id>
<content type='text'>
Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg : Refactor BaseFspCommonLib to reduce binary size</title>
<updated>2024-09-30T08:15:35+00:00</updated>
<author>
<name>Ashraf Ali</name>
<email>ashraf.ali.s@intel.com</email>
</author>
<published>2024-09-08T15:15:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=a6b472131e6f49ec6ec309a06fed3b70b97a8602'/>
<id>urn:sha1:a6b472131e6f49ec6ec309a06fed3b70b97a8602</id>
<content type='text'>
Moved FspApiReturnStatusReset API to a separate file to eliminate
unnecessary inclusion of FspApiReturnStatusReset APIs in driver binary.

When the compiler linking the Object files it may not remove all the
unused from NASM OBJs. This change is to reorganize the C files to
minimize the impact of the NASM behavior resulting is code size
reduction.

Signed-off-by: Ashraf Ali &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Support FSP API to save and restore page table</title>
<updated>2024-09-11T05:45:54+00:00</updated>
<author>
<name>Zhiguang Liu</name>
<email>zhiguang.liu@intel.com</email>
</author>
<published>2024-06-18T08:13:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=14c9ba1a2ca64137de148968823dc20988dcaa4c'/>
<id>urn:sha1:14c9ba1a2ca64137de148968823dc20988dcaa4c</id>
<content type='text'>
A potential issue may happen when FSP creates/changes page table while
bootloader doesn't expect page table being changed in FSP.
Current, FSP API support to save/restore stack, IDT and general purpose
registers. Following the same pattern, add save/restore page table
support to solve this issue.
Note that this feature only impacts FSP API mode, and is controlled
by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD
default value is set as FALSE.

Signed-off-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Align FSP global data pointer for X64 build</title>
<updated>2024-08-28T13:40:56+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2024-07-26T02:16:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=1fd2f9ec8f16cc8efb949888db94eb42006f77c6'/>
<id>urn:sha1:1fd2f9ec8f16cc8efb949888db94eb42006f77c6</id>
<content type='text'>
When it used 32 bits for set FSP global data pointer under X64 build,
it should get FSP global data pointer with 32 bits data under X64 build.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Add get and set FspSmmInit upd data pointer functions</title>
<updated>2023-08-28T21:25:11+00:00</updated>
<author>
<name>Zhang, Hongbin1</name>
<email>Hongbin1.Zhang@intel.com</email>
</author>
<published>2023-08-25T03:15:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=b1e558f6369fc85ae053e0c16ffcd600880fe78d'/>
<id>urn:sha1:b1e558f6369fc85ae053e0c16ffcd600880fe78d</id>
<content type='text'>
FSP-SMM module need get and set FspSmmInit upd data pointer functions
to get and set upd settings.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ray Han Lim Ng &lt;ray.han.lim.ng@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Susovan Mohapatra &lt;susovan.mohapatra@intel.com&gt;
Reviewed-by: S Ashraf Ali &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg/Library/BaseFspCommonLib: Fix OVERRUN Coverity issue</title>
<updated>2023-05-30T05:13:36+00:00</updated>
<author>
<name>Ranbir Singh</name>
<email>rsingh@ventanamicro.com</email>
</author>
<published>2023-05-18T06:28:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=48c53994e649d51a388dc414944c9a9b717a1c3c'/>
<id>urn:sha1:48c53994e649d51a388dc414944c9a9b717a1c3c</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4200

FspData-&gt;PerfIdx is getting increased for every call unconditionally
in the function SetFspMeasurePoint and hence memory access can happen
for out of bound FspData-&gt;PerfData[] array entries also.

Example -
   FspData-&gt;PerfData is an array of 32 UINT64 entries. Assume a call
   is made to SetFspMeasurePoint function when the FspData-&gt;PerfIdx
   last value is 31. It gets incremented to 32 at line 400.
   Any subsequent call to SetFspMeasurePoint functions leads to
   FspData-&gt;PerfData[32] getting accessed which is out of the PerfData
   array as well as the FSP_GLOBAL_DATA structure boundary.

Hence keep array access and index increment inside if block only and
return invalid performance timestamp when PerfIdx is invalid.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Ranbir Singh &lt;rsingh@ventanamicro.com&gt;
Acked-by: Pedro Falcato &lt;pedro.falcato@gmail.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Support 64bit FspResetType for X64 build.</title>
<updated>2022-07-19T22:24:31+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-07-19T03:28:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=140446cd595cad870a0e8cef7a367bae8f09effa'/>
<id>urn:sha1:140446cd595cad870a0e8cef7a367bae8f09effa</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999
FspResetType will be either 32bit or 64 bit basing on
the build type.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: FspSecCore support for X64</title>
<updated>2022-04-16T00:18:14+00:00</updated>
<author>
<name>Ted Kuo</name>
<email>ted.kuo@intel.com</email>
</author>
<published>2022-04-15T08:37:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=00aa71ce20472f0a7bc01e735a0c419adf727def'/>
<id>urn:sha1:00aa71ce20472f0a7bc01e735a0c419adf727def</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FspSecCore support for X64.
2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported.
3.Corrected few typos.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Signed-off-by: Ted Kuo &lt;ted.kuo@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
</feed>
