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<title>Tianocore/edk2.git/IntelFsp2Pkg/Include, branch dependabot/github_actions/actions/setup-python-6</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-6</id>
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<updated>2025-07-16T06:47:27+00:00</updated>
<entry>
<title>IntelFsp2Pkg/FspCommonLib: Remove unused API SetFspCoreStackPointer()</title>
<updated>2025-07-16T06:47:27+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2025-07-14T07:48:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=36b63e9fc87e4494067fb2cfa702449cfbb55b86'/>
<id>urn:sha1:36b63e9fc87e4494067fb2cfa702449cfbb55b86</id>
<content type='text'>
Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg : Add FSP-I arch config PPI</title>
<updated>2024-12-20T07:40:28+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2024-12-17T08:12:20+00:00</published>
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<id>urn:sha1:124ed0f6d83ad5548a4d8f3e436aad0fa4230f76</id>
<content type='text'>
Add FSP-I arch config PPI header file and GUID for supporting FSP-I
to get Bootloader MM FV address and length, Bootloader MM FV context
Data address and length under dispatch mode

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Jiaxin Wu &lt;jiaxin.wu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg : Add fsp status code for fspsmm init</title>
<updated>2024-12-20T06:29:58+00:00</updated>
<author>
<name>Hongbin1 Zhang</name>
<email>hongbin1.zhang@intel.com</email>
</author>
<published>2024-10-07T13:19:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=4ffa8810af6494eacab0898bfcd4cf0d8b49ad5c'/>
<id>urn:sha1:4ffa8810af6494eacab0898bfcd4cf0d8b49ad5c</id>
<content type='text'>
Add fsp status code for fspsmm init interface.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Ray Ni &lt;ray.ni@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Fsp T new ARCH UPD Support</title>
<updated>2024-04-09T17:15:10+00:00</updated>
<author>
<name>Duggapu Chinni B</name>
<email>chinni.b.duggapu@intel.com</email>
</author>
<published>2024-04-05T04:00:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=543add1d414f6016829f7d706fdefb3b830020ef'/>
<id>urn:sha1:543add1d414f6016829f7d706fdefb3b830020ef</id>
<content type='text'>
Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ni Ray &lt;ray.ni@intel.com&gt;

Signed-off-by: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Reviewed-by: Chiu Chasel &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Add get and set FspSmmInit upd data pointer functions</title>
<updated>2023-08-28T21:25:11+00:00</updated>
<author>
<name>Zhang, Hongbin1</name>
<email>Hongbin1.Zhang@intel.com</email>
</author>
<published>2023-08-25T03:15:22+00:00</published>
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<id>urn:sha1:b1e558f6369fc85ae053e0c16ffcd600880fe78d</id>
<content type='text'>
FSP-SMM module need get and set FspSmmInit upd data pointer functions
to get and set upd settings.

Signed-off-by: Hongbin1 Zhang &lt;hongbin1.zhang@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Duggapu Chinni B &lt;chinni.b.duggapu@intel.com&gt;
Cc: Ray Han Lim Ng &lt;ray.han.lim.ng@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Cc: Ted Kuo &lt;ted.kuo@intel.com&gt;
Cc: Ashraf Ali S &lt;ashraf.ali.s@intel.com&gt;
Cc: Susovan Mohapatra &lt;susovan.mohapatra@intel.com&gt;
Reviewed-by: S Ashraf Ali &lt;ashraf.ali.s@intel.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.</title>
<updated>2023-04-04T16:39:41+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2023-03-31T07:09:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546'/>
<id>urn:sha1:af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395

FSP specification defines the TempRamInit API preserved register list
which including EBX/RBX, however current implementation unexpectedly
overriding EBX/RBX register that should be fixed.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Update Function header to support IA32/X64.</title>
<updated>2022-11-02T18:33:31+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-10-28T02:37:27+00:00</published>
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<id>urn:sha1:c46204e25f5b929fae2b336c03c73fada632d4f4</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4126

Common functions will have either 32bit or 64bit instances which
having different return code size. Function header should support both
scenarios.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Fix code formatting errors</title>
<updated>2022-10-04T16:53:59+00:00</updated>
<author>
<name>Michael Kubacki</name>
<email>michael.kubacki@microsoft.com</email>
</author>
<published>2022-09-06T17:45:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=629709a51d76fe6ad22a5441fb979a1b8c9d2e16'/>
<id>urn:sha1:629709a51d76fe6ad22a5441fb979a1b8c9d2e16</id>
<content type='text'>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048

This package did not have CI enabled so code changes were merged
that fail uncrustify formatting. This change updates those files
to include uncustify formatting.

Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Michael Kubacki &lt;michael.kubacki@microsoft.com&gt;
Reviewed-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Michael D Kinney &lt;michael.d.kinney&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.</title>
<updated>2022-08-31T16:48:07+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-07-25T19:03:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=df25a5457f04ec465dce97428cfee96f462676e7'/>
<id>urn:sha1:df25a5457f04ec465dce97428cfee96f462676e7</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Provide FSP 2.4 MultiPhase interface and scripts
support.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
</content>
</entry>
<entry>
<title>IntelFsp2Pkg: FSPI_UPD is not mandatory.</title>
<updated>2022-07-28T16:41:41+00:00</updated>
<author>
<name>Chasel Chiu</name>
<email>chasel.chiu@intel.com</email>
</author>
<published>2022-07-25T19:03:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=3eca64f157c340f9bbf552d89a69698a3090c080'/>
<id>urn:sha1:3eca64f157c340f9bbf552d89a69698a3090c080</id>
<content type='text'>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993
FSPI_UPD is required only When platforms implemented FSP_I component.
Updated the scripts to allow FSPI_UPD not present scenario.
Also fixed FSP_GLOBAL_DATA structure alignment issue and unnecessary
non-backward compatibility change in previous FSP_I patch.

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Star Zeng &lt;star.zeng@intel.com&gt;
Signed-off-by: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Reviewed-by: Star Zeng &lt;star.zeng@intel.com&gt;
</content>
</entry>
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