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<title>Tianocore/edk2.git/BaseTools/Source/C, branch dependabot/github_actions/actions/setup-python-7</title>
<subtitle>EDK II (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2.git/atom?h=dependabot%2Fgithub_actions%2Factions%2Fsetup-python-7</id>
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<updated>2026-07-22T18:06:03+00:00</updated>
<entry>
<title>BaseTools: Add support for preserving build ID</title>
<updated>2026-07-22T18:06:03+00:00</updated>
<author>
<name>Chris Fernald</name>
<email>chfernal@microsoft.com</email>
</author>
<published>2026-01-16T17:30:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=27ac8fac0b61e6b464369cc1cadc66a7b83336c4'/>
<id>urn:sha1:27ac8fac0b61e6b464369cc1cadc66a7b83336c4</id>
<content type='text'>
Adds an optional flag that copies the GNU build-id note from the input
ELF file into the output PE/COFF firmware image as a dedicated ".bldid"
section. The build ID is emitted by the linker as a unique fingerprint
of the binary and allows custom post-build and debugging tools to
reliably match a firmware image against its corresponding unstripped
ELF and debug symbols, without relying on file names, timestamps, or
build paths.

This notable opts to use a non-standard section name ".bldid" to store
the build ID. This approach was chosen to keep genfw and the parsers simple
since the full "build-id" name would require redirecting the section name.
While this breaks from standard conventions, this is not impactful since
GenFW is already creating a non-standard artifact for the PE image with
the associated ELF symbol file.

Signed-off-by: Chris Fernald &lt;chfernal@microsoft.com&gt;
</content>
</entry>
<entry>
<title>BaseTools/GenFv: Preserve legacy rebase behavior when Xip is unused</title>
<updated>2026-07-15T21:37:05+00:00</updated>
<author>
<name>Michael D Kinney</name>
<email>michael.d.kinney@intel.com</email>
</author>
<published>2026-07-14T20:23:03+00:00</published>
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<id>urn:sha1:0347d3b7113ef215e0f19a38206703e86a4e5d1b</id>
<content type='text'>
Add XipFileCount to FV_INFO to track how many files have the ,XIP
suffix. Update FfsRebase() to only apply selective XIP rebase when
XipFileCount &gt; 0. When no files have the ,XIP suffix (XipFileCount
== 0), preserve the legacy ForceRebase=TRUE behavior of rebasing all
files. This maintains backward compatibility for existing platforms
that use FvForceRebase=TRUE without any Xip rules.

Signed-off-by: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
<entry>
<title>BaseTools/GenFv: Parse ,XIP suffix for per-file rebase control</title>
<updated>2026-06-22T15:18:12+00:00</updated>
<author>
<name>Michael D Kinney</name>
<email>michael.d.kinney@intel.com</email>
</author>
<published>2026-05-06T02:10:45+00:00</published>
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<id>urn:sha1:3ee3b60eb82d52e159641b89d66bcc91a40b84ce</id>
<content type='text'>
Update ParseFvInf() to detect and strip ",XIP" suffix from
EFI_FILE_NAME values in the FV INF file. Store the per-file XIP
flag in the new XipFile[] array in the FV_INFO structure.

Add FileIndex parameter to FfsRebase() so it can look up the XIP
flag for the current file. When ForceRebase is TRUE, only rebase
files that have their XipFile[] entry set to TRUE.

Signed-off-by: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
<entry>
<title>BaseTools/GenFw: Fix LoongArch ELF-to-PE RVA conversion</title>
<updated>2026-06-22T03:36:43+00:00</updated>
<author>
<name>Dongyan Qian</name>
<email>qiandongyan@loongson.cn</email>
</author>
<published>2026-06-11T11:58:56+00:00</published>
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<id>urn:sha1:0225975462ae28b2c3ba0bc18cf13f639ab741d9</id>
<content type='text'>
GenFw converts linked ELF images to PE/COFF images using a new section
layout. The generated PE/COFF section RVAs are not required to match the
linked ELF section addresses, so relocation fixups that rewrite section
contents must use the generated PE/COFF RVA space.

A linker script layout change can expose this on LoongArch64 when .text
and .data are linked with 0x1000 alignment while .hii still keeps a
0x4000 alignment. GenFw then keeps a 0x4000 PE/COFF section alignment
because of .hii, producing different ELF and PE/COFF layouts.

Fix two LoongArch relocation paths exposed by this layout mismatch.
R_LARCH_64 entries stored in section contents, such as switch jump
tables, must be translated from the linked ELF section address space to
the generated PE/COFF RVA space. R_LARCH_PCALA_* and R_LARCH_GOT_PC_*
must also convert the referenced symbol to its generated PE/COFF RVA
before calculating the PC-relative offset.

The LoongArch ELF ABI defines PCALA/GOT_PC relocations as page-based,
but this GenFw path rewrites the HI/LO pair to PCADDU12I plus ADDI.D.
After that rewrite, the offset split must be based on the generated
PE/COFF instruction-relative offset.

For example, in the failing LogoDxe image, _gUefiDriverRevision is at
ELF address 0x5400 in .text, and the relocation referencing it is at ELF
address 0x104c. With ELF .text at 0x1000 and PE/COFF .text at 0x4000,
the generated PE/COFF RVAs are 0x8400 for the symbol and 0x404c for the
relocation site. Mixing the ELF symbol address with the PE/COFF
relocation-site RVA makes the entry wrapper read PE/COFF RVA 0x5400
instead of 0x8400, causing EFI_INCOMPATIBLE_VERSION.

Use PE/COFF RVAs consistently when rewriting LoongArch absolute and
PC-relative references during WriteSections64(). The existing
WriteRelocations64() base relocation emission is kept for load-time
image rebasing.

Reported-by: Chao Li &lt;lichao@loongson.cn&gt;
Signed-off-by: Dongyan Qian &lt;qiandongyan@loongson.cn&gt;
Signed-off-by: Chao Li &lt;lichao@loongson.cn&gt;
Tested-by: Dongyan Qian &lt;qiandongyan@loongson.cn&gt;
</content>
</entry>
<entry>
<title>BaseTools: Adjust the LoongArch PC related static relocation</title>
<updated>2026-05-26T13:07:30+00:00</updated>
<author>
<name>Chao Li</name>
<email>lichao@loongson.cn</email>
</author>
<published>2026-05-07T03:26:03+00:00</published>
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<id>urn:sha1:1416dcb8df17f6fb74ec2cf2a881ee8664800af8</id>
<content type='text'>
The relocation methods of R_LARCH_PCALA_HI20, R_LARCH_PCALA_LO12,
R_LARCH_GOT_PC_HI20 and R_LARCH_GOT_PC_LO12 have been optimized to
support cases where HI is not adjacent to LO and where one HI
corresponds to multiple LOs.

Signed-off-by: Chao Li &lt;lichao@loongson.cn&gt;
Cc: Liming Gao &lt;gaoliming@byosoft.com.cn&gt;
Cc: Guillermo Antonio Palomino Sosa &lt;guillermo.a.palomino.sosa@intel.com&gt;
Cc: Yuwei Chen &lt;yuwei.chen@intel.com&gt;
Cc: Poncho Figueroa &lt;poncho.figueroa.esqueda@intel.com&gt;
Cc: Mike Beaton &lt;mjsbeaton@gmail.com&gt;
</content>
</entry>
<entry>
<title>BaseTools: Add missing machine types while dumping Option Rom</title>
<updated>2026-04-23T05:31:47+00:00</updated>
<author>
<name>Qihang Gao</name>
<email>gaoqihang@loongson.cn</email>
</author>
<published>2026-04-20T06:24:53+00:00</published>
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<id>urn:sha1:5e2bea1a7453dddeaa83840a4b974bb94d3e4f9c</id>
<content type='text'>
When dumping LOONGARCH64 or RISCV64 Option Rom by `EfiRom -d test.rom`
command, the machine type is showed as `unknown`. This patch adds type
lookup strings for the two architectures.

Signed-off-by: Qihang Gao &lt;gaoqihang@loongson.cn&gt;
</content>
</entry>
<entry>
<title>BaseTools: Enable control flow guard for Windows builds</title>
<updated>2026-03-26T02:28:23+00:00</updated>
<author>
<name>Kun Qin</name>
<email>kuqin@microsoft.com</email>
</author>
<published>2026-03-17T18:37:12+00:00</published>
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<id>urn:sha1:ef23e3c9e726edd714b2091657e8fad1a35eb325</id>
<content type='text'>
Certain environments require Control Flow Guard (CFG) to be enabled at
build time as part of their security hardening requirements.

This change adds the necessary compiler and linker flags to enable CFG
support.

Signed-off-by: Kun Qin &lt;kun.qin@microsoft.com&gt;
</content>
</entry>
<entry>
<title>BaseTools: Suppress C4028 warning to support older VS toolchain builds</title>
<updated>2026-03-26T02:28:23+00:00</updated>
<author>
<name>Kun Qin</name>
<email>kuqin@microsoft.com</email>
</author>
<published>2026-03-16T21:48:04+00:00</published>
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<id>urn:sha1:4e0376c48b1738da5539801458bfa70ad43bc53e</id>
<content type='text'>
Add conditional suppression of MSVC warning C4028 (formal parameter
different from declaration) when building with Visual Studio 2017 or
earlier toolchain.

This warning is triggered by brotli submodule and not emitted by newer
compilers, hence a conditional supression is used.

Signed-off-by: Kun Qin &lt;kun.qin@microsoft.com&gt;
</content>
</entry>
<entry>
<title>BaseTools: GenFfs/GenFv/GenSec: Fixing Warning 4319 from MSVC</title>
<updated>2026-03-13T19:14:49+00:00</updated>
<author>
<name>Kun Qin</name>
<email>kuqin@microsoft.com</email>
</author>
<published>2026-03-10T08:06:00+00:00</published>
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<id>urn:sha1:8c298e11045e95d9ef40dedc3e6a37eb2625487a</id>
<content type='text'>
This change fixes a warning newly emitted by the latest MSVC, which now
treats this warning as an error and causes the build to fail.

This change aligns operand types in bitwise expressions by casting sizeof
results to UINT32, and promoting a UINT32 to UINTN where required to
correctly apply the bitmask.

Signed-off-by: Kun Qin &lt;kun.qin@microsoft.com&gt;
</content>
</entry>
<entry>
<title>BaseTools/Source/C/Include/Common: Add back include guard</title>
<updated>2026-02-27T07:15:11+00:00</updated>
<author>
<name>Michael D Kinney</name>
<email>michael.d.kinney@intel.com</email>
</author>
<published>2026-02-25T20:53:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2.git/commit/?id=3eb2ff24b9fe5c0ea8d543e1deb7c6efac610655'/>
<id>urn:sha1:3eb2ff24b9fe5c0ea8d543e1deb7c6efac610655</id>
<content type='text'>
Add include guards back to include files that use the same
include guard macro in BaseTools/Source/C/Include/Common
and MdePkg or MdeModulePkg.

Signed-off-by: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
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