Tianocore/edk2.git/ArmPlatformPkg/Sec, branch dependabot/github_actions/actions/setup-python-6

ArmPlatformPkg: Introduce gArmTransferListPpiGuid

2025-07-24T05:59:45+00:00

Populate the gArmTransferListPpiGuid with the TransferList base address. Place the Ppi at the end of the PpiList For platforms with no TransferList support, boot continues without any errors. https://firmwarehandoff.github.io/firmware_handoff Signed-off-by: Prachotan Bathi

ArmPlatformPkg: Capture TransferList Information for SEC

2025-07-24T05:59:45+00:00

Capture TransferList address from register x3 Refer to section 3 of the FW Handoff Specification https://firmwarehandoff.github.io/firmware_handoff The TransferList header is present at the base address captured by this variable. For platforms with no TransferList support, boot continues without any errors. Signed-off-by: Prachotan Bathi

ArmPlatformPkg/Sec: Re-use SetupExceptionLevel1 when running VHE at EL2

2025-05-28T19:09:22+00:00

Given that CPACR_EL1 is aliased to CPTR_EL2 when running at EL2 with VHE enabled, we can just fall back to SetupExceptionLevel1() instead of fiddling with the init values for CPTR_EL2. While at it, use the existing define to refer to the E2H bit in HCR_EL2. Signed-off-by: Ard Biesheuvel

ArmPlatformPkg/Sec: Simplify SetupExceptionLevel1() using a tail call

2025-05-28T19:09:22+00:00

Avoid a call and use a jump instead, so that the LR value does not need to be recorded in a different register. This is generally neater, but it also avoids potential confusion in the debugger, given that no frame record is created for this call. Signed-off-by: Ard Biesheuvel

ArmPlatformPkg/Sec: Remove EL1 timer setup when booting at EL2

2025-05-28T19:09:22+00:00

Even though the UEFI spec mentions that the EL1PCTEN and EL1PCEN bits in CNTHCTL_EL2 must be set, this is not a requirement that applies to the UEFI implementation, but a requirement that applies to the firmware running at EL2 in cases where UEFI executes at EL1. (Note that the same paragraphs mentions that CNTFRQ must be programmed with the timer frequency, and this is only permitted at EL3). Setting these bits has no effect when executing at EL2, and it is the OS's job to reason about how to configure lower exception levels. So drop the initialization of CNTHCTL_EL2. Signed-off-by: Ard Biesheuvel

ArmPlatformPkg/Sec: Deal with entry at EL2 with VHE enabled

2025-05-27T15:12:31+00:00

The architecture now permits HCR_EL2.E2H to be RES1, and so even though the UEFI spec is silent on the matter, entering at EL2 with VHE enabled is a condition that needs to be dealt with. In particular, virtual machines running under nested virtualization on Apple M2 or newer will enter in this manner In this case, the CPTR_EL2 system register needs to be treated as if its layout is identical to CPACR_EL1. Not doing so may result in all kinds of surprises, but the most noticeable is an early crash on the use of FP/SIMD registers, which get disabled inadvertently by this code. Signed-off-by: Ard Biesheuvel

ArmPlatformPkg/Sec: clean up FP enabling code

2025-04-11T12:48:56+00:00

UEFI defines that FP support is required on AArch64, whereas many platforms enable it anyway on Arm. But when it's enabled, C code can generate instructions targeting FP registers, so: - move ArmEnableVFP call to asm - make it unconditional on AArch64 Signed-off-by: Leif Lindholm

MdePkg: Move StackCheckLibStaticInit to StackCheckLib

2025-02-07T02:23:11+00:00

This commit oves StackCheckLib from a NULL lib to an instance of StackCheckLib. This requires every entry point to add a library dependency on StackCheckLib. It also requires every SEC module to have a dependency on StackCheckLib because there is no standard SEC entry point. It allows for greater flexibility for a platform to apply stack cookies and simplifies DSC logic. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Oliver Smith-Denny

ArmPlatformPkg: Honour RES1 fields in CPTR_EL2

2024-11-14T06:25:27+00:00

Unlike CPACR_EL1 whose reserved bits are solely RES0, CPTR_EL2 has some RES1 bits, and so we should not clear them unless we know what they mean. For example, when SVE was introduced, CPACR_EL1.ZEN occupied a RES0 field and thus 0 means trap (which is what we get at EL1), but CPTR_EL2.TZ occupied a RES1 field and thus 1 means trap, but we set it to 0, so the environment is inconsistent between EDK2 and EL1 and EL2. Another concrete case is for Morello, where the CEN/TC fields similarly gate access to capability register state, but also alter exception delivery and return, such that VBAR_ELx and ELR_ELx become capabilities. So long as software adheres to RES0/1 this is backwards-compatible, but since EDK2 does not do so here it inadvertently enables capability-based exception delivery and return and thus, when run at EL2, gets stuck in a trap loop when taking its first interrupt, but works just fine at EL1. Fix this by setting all the RES1 fields in CPTR_EL2, following the pattern for CPACR_EL1's non-zero initial value (due to setting FPEN so as to not trap on SIMD/FP use), tested by running ArmVirtQemu-AARCH64 (DEBUG) on Morello QEMU with EL2 enabled. Signed-off-by: Jessica Clarke

ArmPlatformPkg,MdePkg: Rename AARCH64 CPACR_CP_FULL_ACCESS

2024-11-14T06:25:27+00:00

CP_FULL_ACCESS is a misnomer, we only enable access to SIMD/FP state, and although the register's mnemonic is CPACR_EL1, its full name is "Architectural Feature Access Control Register", with AArch64 having no coprocessors like AArch32 did, so the "CP" is also not appropriate. Rename it to show it's the default value we use on entry, and define it in terms of the existing CPACR_FPEN_FULL rather than a magic constant with the same value to more clearly document that fact. Also update comments to reflect all this (including the CPTR_EL2 case). Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Jessica Clarke