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2023-11-16Silicon/Marvell: Restructure packageNarinder Dhillon5-65/+65
Current Marvell package structure makes it difficult to add new silicon packages that reuse common elements without creating nested DEC files. This patch creates a new MarvellSiliconPkg folder and moves the current common elements inside it. Also gMarvellTokenSpaceGuid has been renamed to gMarvellSiliconTokenSpaceGuid to align with new package name. Signed-off-by: Narinder Dhillon <ndhillon@marvell.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2021-08-02Marvell: IcuLib: Rework default interrupt mapMarcin Wojtas2-87/+34
The ICU to GIC interrupt mapping was fixed to support the maximum of two CP11x south bridge units. Rework the default map to use only the interrupts wired to controllers supported in the ACPI tables. Thanks to above all necessary IRQs from the CN913x SoCs (maximum 3 CP11x) can be mapped and passed to the OS. Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2020-05-19Marvell/Library: UtmiLib: Fix USB mux configurationMarcin Wojtas1-0/+1
If UTMI connected to USB Device, the MUX must be configured prior to the PHY init. Add missing register update in the relevant code. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2020-05-19Marvell/Library: UtmiLib: Fix pll initialization for the second portMarcin Wojtas2-10/+22
According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This fixes issues in scenarios when only UTMI port1 was in use, which resulted with lack of correct PLL initialization. On the occasion add relevant comments, describing the register groups in the header file. Based on original change from Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2020-05-19Marvell/Library: UtmiLib: Update USB2.0 analog settingsMarcin Wojtas2-5/+23
This patch introduce following modifications, allowing to overcome the instabilities observed with certain USB2.0 endpoints: * Add additional step which enables the Impedance and PLL calibration. * Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. * Update LS TX driver strength coarse and fine adjustment values. Based on original change from Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2019-10-14Marvell/Library: IcuLib: Fix debug informationMarcin Wojtas1-2/+2
In case the number of CP11x components exceeded the maximum of currently supported, the user is informed with the information. It turned out that the print arguments were incorrect - fix it. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-10-14Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon informationMarcin Wojtas1-3/+1
Hitherto SoC description and MppLib libraries code assumed that there could be only two Xenon SdMmc controller instances in the SoC. Remove those limitations, so that to support CN913x SoCs, which may have up to 4 of such interfaces. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-07-29Silicon/Marvell: Replace BSD License with BSD+Patent LicenseMichael D Kinney10-280/+10
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Email thread with approval from Marvell: https://edk2.groups.io/g/devel/message/41507 Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Marcin Wojtas <mw@semihalf.com>
2019-05-18Silicon/Marvell: Replace BSD License with BSD+Patent LicenseMichael D Kinney5-35/+5
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html NOTE: Files with a BSD 3-Clause license are not modified by this patch series. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-04-20Marvell/Library: ComPhyLib: Update mode parameter for PCIE power onMarcin Wojtas1-1/+3
Most recent ARM-TF ComPhy PCIE initialization routines check additional mode parameter in order to determine, where the SMC is called from (OS / firmware). Adjust to that. This patch fixes the Linux boot with DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2019-01-30Marvell/Library: Introduce common header for the SMC ID'sMarcin Wojtas2-12/+10
Marvell firmware allows to use SiP services other than for ComPhy handling. In order to avoid spreading the SMC ID's definitions across many files, introduce common header for that purpose. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-01-17Marvell/Library: Introduce MvGpioLibMarcin Wojtas2-0/+164
Following patches will add two drivers that are capable of producing the generic EMBEDDED_GPIO protocol. In order to handle a situation, when the consumer module attempts to locate and open a proper protocol, add a library helper function. In order to ease description of used GPIO pins and controllers of the Armada 7k8k platforms, add the common enum types. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-01-17Marvell/Library: ArmadaSoCDescLib: Add GPIO informationMarcin Wojtas3-0/+3
This patch introduces new library callback (ArmadaSoCGpioGet ()), which dynamically allocates and fills EmbeddedGpio's GPIO_CONTROLLER structure with the SoC description of GPIO controllers. Because the library header is indirectly used in many modules, update all dependencies after including EmbeddedGpio.h. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2018-08-02Marvell/Library: ComPhyLib: Clean up the library after reworkGrzegorz Jaszczyk2-516/+0
Because all ComPhy related initialization was moved to ARM-TF all register definitions and some related routines/structures became unused. This commit removes them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-08-02Marvell/Library: ComPhyLib: Remove both PHY and PIPE selector configGrzegorz Jaszczyk4-237/+0
Now the ComPhy configuration is handled in ARM-TF, therefore there is no need to configure PHY or PIPE selector in UEFI. Remove unused code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-08-02Marvell/Library: ComPhyLib: Configure USB in ARM-TFGrzegorz Jaszczyk1-163/+4
Replace the comphy initialization for USB with appropriate SMC call, so the ARM-TF will execute required serdes configuration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-08-02Marvell/Library: ComPhyLib: Configure RXAUI in ARM-TFGrzegorz Jaszczyk2-253/+5
Replace the comphy initialization for RXAUI with appropriate SMC call, so the ARM-TF will execute required serdes configuration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-08-02Marvell/Library: ComPhyLib: Configure PCIE in ARM-TFGrzegorz Jaszczyk2-485/+8
Replace the ComPhy initialization for PCIE with appropriate SMC call, so the ARM-TF will execute required serdes configuration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-08-02Marvell/Library: ComPhyLib: Configure SATA, SGMII and SFI in ARM-TFGrzegorz Jaszczyk5-740/+143
Because it is now available to configure SerDes lanes via SiP services in the EL3, there is no need to maintain same code within UEFI. This patch reworks serdes for: SATA, SGMII, HS-SGMII and SFI interfaces. The next interfaces will be addressed in upcoming commits. Parameters' description used in .dsc files and the ComPhyLib were aligned to the ones used in EL3. For this purpose and additional header was created. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-07-25Marvell/Library: Implement common ArmadaIcuLibMarcin Wojtas3-0/+402
ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send-message based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GICv2 of the Armada7k8k SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-06-21Marvell/Library: ComPhyLib: Switch library to use MARVELL_BOARD_DESCMarcin Wojtas1-29/+45
MvComPhyLib library used to get Armada7k8k SerDes multiplexing controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the library, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2018-06-21Marvell/Library: ComPhyLib: Get AHCI data with MARVELL_BOARD_DESCMarcin Wojtas3-25/+35
ComPhy Library used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the driver to get AHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2018-06-21Marvell/Library: UtmiPhyLib: Switch to use MARVELL_BOARD_DESC protocolMarcin Wojtas3-49/+30
UTMI driver used to get Armada7k8k UTMI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get UTMI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Use the protocol and pass information to further to the library init routine. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2018-05-22Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2Evan Wang4-50/+201
PCIE clock direction (input/output) has implications on comphy settings. There are 2 PCIe clocks in CP110: - Ref clock 0 for lanes 1, 2 and 3 - Ref clock 1 for lanes 4 and 5 A proper handling of above had to be added, using newly introduced sample at reset library class for Marvell SoCs. Other than that, update HPIPE settings and the reset sequence, which differ from one used in x1 link. This patch fixes PCIE x4 and x2 configuration, which helps to overcome link establishing issue for multi-lane end points. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Evan Wang <xswang@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-12-08Marvell: Reorganize file structureMarcin Wojtas10-0/+3836
In edk2-platforms it is expected to provide a separation between SoC and boards files in 'Silicon' and 'Platform' directories accordingly. This patch aligns Marvell code to this requirement with no functional changes in the actual source files, unless required due to modified paths. Change the supported board's files names to proper Armada70x0Db. Also rename 'Armada' directory to 'Armada7k8k' in order to properly refer to the SoC family and prevent confusion in future, when adding new Armada machines. On the occasion add ARM copyright, which was wrongly missing in the dsc.inc file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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