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Removes AcpiCommon driver.
Driver is split into multiple libraries and
moved under AmdPlatformPkg/DynamicTables folder.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Remove the ACPI table patching code.
All required AMD ACPI tables will be installed
by AmdPlatformPkg.
Hence no need to patch the ACPI tables.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Creates ACPI FADT table during boot time.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Creates ACPI MCFG table during boot time.
Adds a library to generate and install MCFG table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Creates MADT/APIC table during boot time.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Generates ACPI SSDT PCI topology.
Append the PCI SSDT tolology to the DSDT table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Create ACPI SSDT CPU toplogy.
Append the CPU SSDT topology to the DSDT table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Set PcdAcpiBaseAddress to 0x400 for PEI MM communication.
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
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Install an instance of EFI_PEI_MM_CONTROL_PPI.
This PPI provides a standard way for other modules to
trigger software SMIs.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
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This patch is to add SmmControlLib.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
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Do the smm relocation during platform init.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
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This patch is to add SmmRelocationLib for SMM CPU driver usage.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
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By default we have Neoverse-N2 cpu which supports FEAT_RNG feature. This
allows us to add RngDxe to have EFI_RNG_PROTOCOL available on
Neoverse-N2 and 'max' cpu cores.
Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
ArmVirt platform.
RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by QEMU.
Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.
TRNG is not implemented in TCG mode but is required by RngDxe to run.
On older cpu cores nothing changes.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
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The freedom unleashed platform currently fails to build due to a
missing mapping for RiscVMmuLib, so add one.
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Abner Chang <abner.chang@amd.com>
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Abner Chang <abner.chang@amd.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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Adds a library to generate and install FACS table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Adds a library to generate and install SPMI table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Adds a library to generate and install WSMT table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Adds a library to generate and install HPET table.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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This patch is to enable the PcdSmrrEnable since the simics
report it has the capability to enable the smrr.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
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Some Arm ltd. platforms explicitly set PcdArmArchTimerFreqInHz, however
the intended effect of that is not possible from AArch64 EL2/1, and has
never been performed unless built for ARM.
The Pcd is now being deleted, so drop the setting.
This has however affected timer timout calculations, so could lead to a
change in platform behaviour.
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.
Reformat all files to make new contributions easier. We can recommend
formatting sources without generating extra work for developers.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
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PcdArmArchTimerFreqInHz is about to be removed, as it is now obsolete.
Some platforms already explicitly set it to 0, which is the default.
And some modules reference it in their .inf without actually ever
using it.
Drop these redundant uses first.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: Nhi Pham <nhi@os.amperecomputing.com>
Cc: Rebecca Cran <rebecca@os.amperecomputing.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Wenyi Xie <xiewenyi2@huawei.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com>
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A patch adding a mapping for ImagePropertiesRecordLib introduced a bunch of
LF line endings in otherwise CRLF files, so clean that up.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: Marcin Wojtas <marcin.s.wojtas@gmail.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: Narinder Dhillon <ndhillon@marvell.com>
Cc: Nhi Pham <nhi@os.amperecomputing.com>
Cc: Rebecca Cran <rebecca@os.amperecomputing.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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QEMU no longer permits misaligned access to device memory, which breaks
QemuVideoDxe on SbsaQemu.
c1d1910be6e04a8b1a73090cf2881fb698947a6e commit in EDK2 fixed it by
enabling WriteCombine for Framebuffer memory. This change enables that
fix.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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Temparory stack memory on PEI is hardcoded now, also minimium memory
size 256M is hardcoded now. Here memory map table from fw cfg can be
parsed. If there is memory map entry contains pei stack, it can be
published as usable memory at PEI stage.
Cc: Bibo Mao <maobibo@loongson.cn>
Cc: Chao Li <lichao@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Reviewed-by: Chao Li <lichao@loongson.cn>
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Implements SpiHcPlatformLib library for AMD platform.
Its AMD platform specific SPI host controller library.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The PcdL2CacheSize PCD specifies the size of L2 cache of the
CPU. Use the size specified by this PCD in the PPTT table of
the RD-N2 platform.
The size of the CPU's L2 cache can be configured at build time
using the --pcd command line option of the build command.
e.g. To set the L2CacheSize to 2MB specify the pcd option as:
$ build ... -p <DSC file> --pcd PcdL2CacheSize=0x200000
This allows changing the value of the L2 cache size depending
the variant of the RD-N2 platform being build. RD-V2 platform
is an example of such a variant.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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A new PCD named PcdL2CacheSize is introduced to specify the size of the
CPU's L2 cache. This PCD can be used in PPTT tables for a reference
design platform. The default value of this PCD is set to 1MB but can be
changed depending on the variant of the reference design platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Implements SPI firmware volume driver for SPI.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Adds BoardSpiConfig DXE and SMM driver.
This driver installs EFI_SPI_CONFIGURATION_PROTOCOL protocol.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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Implements PlatformSecLib Library for AMD platforms.
Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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This driver enables Fault Tolerant Write protocol, which provides
fault tolerant write capability for block devices.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Enable persistent storage on QSPI flash device.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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In N1Sdp platform, the SoC is connected to IOFPGA which has a
Cadence Quad SPI (QSPI) controller. This QSPI controller manages
the flash chip device via QSPI bus.
This patch adds CadenceQspiNorFlashDeviceLib which is used to
manage and access the above configuration.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds an optional functionality in NorFlashDxe to fetch and
print NOR Flash information from NorFlashInfoLib using its JEDEC ID.
NOR Flash libraries will implement a function "NorFlashReadID" which
will fetch and return JEDEC ID. This JEDEC ID can be then printed
along with the NOR Flash info by NorFlashInfoLib. If this functionality
is not needed then the function can just return EFI_UNSUPPORTED.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds error_handler1 and error_handler2 labels in
NorFlashCreateInstance() function to handle the cleanup.
error_handler1: Frees just the Instance structure as the
ShadowBuffer is not allocated yet.
error_handler2: Frees both Instance and Instance->ShadowBuffer.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This variable holds the QSPI controller's base address.
It is defined in ARM.dec as well with the default value of 0x0.
In case a platform is not using it, they can just ignore this
variable and the default value of 0x0 will be propogated and
the variable will not be used.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch adds the following major changes:
1. Adds changes in NorFlashDxe to look for NorFlashDeviceLib instead of
NorFlash.c for flash specific implementation
2. Remove NorFlash.c and NorFlash.h as they are no longer required.
3. Add changes to platform description files to provide
P30NorFlashDeviceLib as NorFlashDeviceLib
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch implements functions to interact with P30 NOR Flash.
The code is taken from Platform/ARM/Drivers/NorFlashDxe/NorFlash.c
file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch splits NorFlash.h and moves out the function prototypes and
macros that are expected by NorFlashDxe to be implemented by any
Nor Flash implementation to NorFlashDeviceLib.h file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch makes local functions not being used outside
NorFlash.c STATIC.
Also, NorFlashWriteBuffer() is specific to a particular
flash implementation and need not be implemented by
other NOR flash device IPs.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch removes NorFlashReadCfiData() and NorFlashWrite()
prototypes from NorFlash.h as these are not implemented or
used anywhere in NorFlashDxe driver.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Refactoring done in this patch has two major parts:
1. Moving out NorFlashUnlockAndEraseSingleBlock and
NorFlashWriteFullBlock functions from NorFlashDxe.c and
NorFlashStandaloneMm.c to NorFlash.c files.
2. At the same time, we are adding NorFlashLock and NorFlashUnlock
functions which will take care of TPL related operations needed by
functions mentioned in point 1. These functions are implemented
in NorFlashDxe.c but are just dummy placeholder functions in
NorFlashStandaloneMm.c file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch splits NorFlash.h and adds NorFlashCommon.h which
will have all the flash independent functions and macros.
Whereas all the flash specific functions will be in NorFlash.h
header file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Moving this function from NorFlash.c to NorFlashDxe.c as it is not
dependent on any particular flash implementation.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Moving these functions from NorFlash.c to NorFlashBlockIoDxe.c as
they are not dependent on any particular flash implementation.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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