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2023-04-17Platform/Siliocn: Fix building failure caused by wrong lib.Evan Chai3-3/+8
RiscVSbiLib was implemented in MdePkg/Library/BaseRiscVSbiLib. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Evan Chai <evan.chai@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2023-01-05Platform/RISC-V/PlatformPkg: Fix image link errorSunil V L1-6/+6
The serial number of Edk2OpensbiPlatformWrapperLib Library and RiscVSpecialPlatformLib Library in the figure is opposite to the text description. Fix it and adjust the text order. Signed-off-by: Dongdong Zhang <zhangdongdong@eswincomputing.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18RISC-V/PlatformPkg: Address Core CI Uncrustify errorsAbner Chang21-635/+745
Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18RISC-V/PlatformPkg: Address Core CI library header check errorsAbner Chang1-0/+2
Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18RISC-V/PlatformPkg: Address Core CI license check errors.Abner Chang1-6/+5
Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18RISC-V/PlatformPkg: Address Core CI package dependency check errorsAbner Chang1-1/+0
Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18RISC-V/PlatformPkg: Address Spelling check errors.Abner Chang12-37/+37
Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18RISC-V/PlatformPkg: Address ECC errorsAbner Chang30-106/+232
Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2022-02-18PlatformPkg/PlatformPei: Fix the build errorAbner Chang3-10/+14
Fix the build error caused by the dependency with SiFive silicon code. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-23Platform/RISC-V: Initialize variable to zeroAbner Chang1-1/+1
Initialize variable NumberOfPlatformInArray to 0. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-11-23Platform/RISC-V: Add debug message to SecMain.cAbner Chang1-1/+13
Add more debug messages when search FFS in SEC phase. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-11-10RISC-V/PlatformPkg: Determine hart number from DTBAbner Chang4-27/+49
Determine total number of hart from DTB instead of using PCD. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook.Abner Chang9-426/+598
Separate EDK2 Opensbi platform operations hooks from Secmain as an individual library which can be override by OEM platform. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RISC-V/PlatformPkg: Updates for the latest OpenSBIAbner Chang6-356/+212
Code changes to incorporate with OpenSBI commit ID: a731c7e36988c3308e1978ecde491f2f6182d490 Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RiscVPlatformPkg/Sec: Add more comments to Secmain.cAbner Chang1-3/+6
Add more comments to SecMain.c Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RiscVPlatformPkg/Sec: Check Cold/Warm hartAbner Chang1-1/+14
Check Coldboot or Warmboot hart in SEC OpenSBI platform function. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module nameAbner Chang3-3/+4
Rename RiscVSpecialPlatformLib to RiscVSpecialPlatformLibNull because this is the NULL instance for RiscVPlatformPkg. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RiscVPlatformPkg/OpensbiPlatformLib: Remove platform codeAbner Chang1-18/+7
Remove platform code from generic OpensbiPlatfomLib. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RiscVPlatformPkg/Sec: Initial hart_index2Id arrayAbner Chang5-13/+96
Initial hart index to Id array by invoking OpenSBI fw_platform_init function. Introduce PcdBootableHartIndexToId PCD which could be used to overwrite the hart_index2Id arrary built from Devie tree according to platform demand. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNullAbner Chang3-90/+1
Remove Null instance of OpensbiPlatformLibNull, OpensbiPlatformLib is the generic one for RsicVPlatformPkg. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10Platform/RISC-V: Remove platform dependency from common platform libAbner Chang4-86/+19
This is the generic library for all RISC-V platforms. Remove the dependencies of SiFive U540 platform. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLibAbner Chang4-0/+77
This is the library instance to provide platform_override for the special RISC-V platform. This module incorporates with OpensbiPlatformLib and RISC-V Opensbi library. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10Platform/RISC-V: Use PlatformSecPpiLibAbner Chang5-107/+14
Use PlatformSecPpiLib to get PPI descriptor and remove PPI descriptor related code from SEC. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10Platform/RISC-V: Add library to get PPI descriptorAbner Chang4-0/+90
The library to provide the platform PPI descriptors in PEI core entry before executing PEI core. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RISC-V: Use RISC-V PeiCoreEntryPoint libraryAbner Chang4-50/+540
1. Use RISC-V PeiCoreEntryPoint library instance for opensbi to switch to the next phase with arg0 as HART Id and arg1 as the SEC to PEI handoff data. 2. Introduce EDK2 opensbi platform operation functions. With this, OEM can has its won platform initialization code before and/or after opensbi vendor platform functions. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RISC-V: Create opensbi firmware domainsAbner Chang6-75/+124
Incorporate with opensbi to create three firmware domains, - Boot firmware domain, which built with opensbi library as M-mode access only region. - Firmware domain which includes PEI and DXE regions, the PMP attribute is readable, wriable and executable. - EFI Variable region which is readable and writable. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RISC-V: Add RISC-V PeiCoreEntryPoint libraryAbner Chang4-1/+153
- Add RISC-V PeiCoreEntryPoint library that incorporates with opensbi next phase switching mechanism. - Use RiscVFirmwareContext library to get the pointer of opensbi FirmwareContext. Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-11-10RISC-V/PlatformPkg: Update documentAbner Chang3-14/+3336
Update EDK2 RISC-V port architectural diagrams. Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
2021-10-19Move OpenSbiPlatformLib to RISC-V/PlatformPkgDaniel Schaefer4-0/+357
It's a generic platform file. Only the device tree decides what happens. Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19RISC-V: Implement ResetSystem RT callDaniel Schaefer2-0/+161
Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19RISC-V: Switch to latest OpenSBIDaniel Schaefer3-12/+22
Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOBAbner Chang2-0/+119
Cc: Daniel Schaefer <daniel.schaefer> Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19RISC-V/PlatformPkg: Build DeviceTree and use that in SECDaniel Schaefer4-22/+55
OpenSBI uses the device tree for platform specific initialization, so we need to have it already in SEC. Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19RISC-V: Use U5 SMBIOS library only for those platformsDaniel Schaefer3-1/+81
Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19RISC-V: Split SMBIOS out of PlatformPeiDaniel Schaefer1-16/+1
Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19U5SeriesPkg: Deduplicate PlatformPeiDaniel Schaefer5-0/+606
The current (and future) RISC-V platforms share a lot of PlatformPei code that does not need to be duplicated. If we see that they need to have different behavior in the future, we can add platform specific libraires for that specific code. The upcoming RiscvVirt is only 1205 lines with this patch. Still way too much. Hopefully MinPlatform will help. 26 ./RiscvVirt.dec 13 ./RiscvVirt.uni 12 ./RiscvVirtPkgExtra.uni 78 ./VarStore.fdf.inc 66 ./RiscvVirt.fdf.inc 654 ./RiscvVirt.dsc 356 ./RiscvVirt.fdf 1205 total Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-10-19Signal EndOfDxe in boot managerDaniel Schaefer2-2/+8
Otherwise we can't load a 3rd party image because we're still in DXE. MdeModulePkg/Universal/SecurityStubDxe/Defer3rdPartyImageLoad.c prevents that. Cc: Abner Chang <abner.chang@hpe.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
2021-03-31Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLibDandan Bi1-0/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 MdeLibs.dsc.inc was added for some basic/default library instances provided by MdePkg and RegisterFilterLibNull Library was also added into it as the first version of MdeLibs.dsc.inc. So update platform dsc to consume MdeLibs.dsc.inc for RegisterFilterLibNull which will be consumed by IoLib and BaseLib. Cc: Abner Chang <abner.chang@hpe.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Abner Chang <abner.chang@hpe.com>
2020-10-02Silicon/SiFive: Handle case of NULL FirmwareContextAbner Chang1-3/+8
Abort creating the SMBIOS HOBs if there's no firmware context to get the information from. Turn SbiLib functions for getting mscratch into VOID since they can never practically fail. Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com>
2020-08-29RISC-V/PlatformPkg: Revise Readme.mdAbner Chang1-36/+52
Update RISC-V PlatformPkg Readme.md to align with the latest implementation. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
2020-08-23PlatformPkg: Add RiscVPlatformPkgAbner Chang5-0/+289
Add RISC-V platform package. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/SecMain: RISC-V SecMain module.Abner Chang4-0/+1399
SecMain module for RISC-V platform. This was cloned from OpenSBI fw_base.S (RiscVPkg/Library/RiscVOpensbiLib/opensbi/firmware/) and revised to edk2 framework. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/PlatformBootManagerLib: Platform Boot Manager library.Abner Chang5-0/+498
Common Platform Boot Manager library for RISC-V platform. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/PlatformUpdateProgressLibNull: NULL instance ofAbner Chang2-0/+81
PlatformUpdateProgressLib NULL instance of PlatformUpdateProgressLib. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/PlatformMemoryTestLibNull: NULL instance ofAbner Chang2-0/+58
PlatformMemoryTestLib NULL instance of PlatformMemoryTestLib. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/OpensbiPlatformLibNull: NULL instance of RiscVOpensbiPlatformLibAbner Chang2-0/+82
NULL instance of RiscVOpensbiPlatformLib. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/FirmwareContextProcessorSpecificLib:Add ↵Abner Chang3-0/+203
FirmwareContextProcessorSpecificLib module Add OpenSBI firmware context processor specific library which provides interface to create processor specific firmware context hob data. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-08-23PlatformPkg/RiscVPlatformTempMemoryInit:Abner Chang3-0/+81
RISC-V Platform Temporary Memory library NULL instance of RISC-V Platform Temporary Memory library. Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-09-30 22:35:31 +0300