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Some Arm ltd. platforms explicitly set PcdArmArchTimerFreqInHz, however
the intended effect of that is not possible from AArch64 EL2/1, and has
never been performed unless built for ARM.
The Pcd is now being deleted, so drop the setting.
This has however affected timer timout calculations, so could lead to a
change in platform behaviour.
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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PcdArmArchTimerFreqInHz is about to be removed, as it is now obsolete.
Some platforms already explicitly set it to 0, which is the default.
And some modules reference it in their .inf without actually ever
using it.
Drop these redundant uses first.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: Nhi Pham <nhi@os.amperecomputing.com>
Cc: Rebecca Cran <rebecca@os.amperecomputing.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Wenyi Xie <xiewenyi2@huawei.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com>
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A patch adding a mapping for ImagePropertiesRecordLib introduced a bunch of
LF line endings in otherwise CRLF files, so clean that up.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Graeme Gregory <graeme@xora.org.uk>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cc: Marcin Wojtas <marcin.s.wojtas@gmail.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: Narinder Dhillon <ndhillon@marvell.com>
Cc: Nhi Pham <nhi@os.amperecomputing.com>
Cc: Rebecca Cran <rebecca@os.amperecomputing.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The PcdL2CacheSize PCD specifies the size of L2 cache of the
CPU. Use the size specified by this PCD in the PPTT table of
the RD-N2 platform.
The size of the CPU's L2 cache can be configured at build time
using the --pcd command line option of the build command.
e.g. To set the L2CacheSize to 2MB specify the pcd option as:
$ build ... -p <DSC file> --pcd PcdL2CacheSize=0x200000
This allows changing the value of the L2 cache size depending
the variant of the RD-N2 platform being build. RD-V2 platform
is an example of such a variant.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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A new PCD named PcdL2CacheSize is introduced to specify the size of the
CPU's L2 cache. This PCD can be used in PPTT tables for a reference
design platform. The default value of this PCD is set to 1MB but can be
changed depending on the variant of the reference design platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This driver enables Fault Tolerant Write protocol, which provides
fault tolerant write capability for block devices.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Enable persistent storage on QSPI flash device.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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In N1Sdp platform, the SoC is connected to IOFPGA which has a
Cadence Quad SPI (QSPI) controller. This QSPI controller manages
the flash chip device via QSPI bus.
This patch adds CadenceQspiNorFlashDeviceLib which is used to
manage and access the above configuration.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds an optional functionality in NorFlashDxe to fetch and
print NOR Flash information from NorFlashInfoLib using its JEDEC ID.
NOR Flash libraries will implement a function "NorFlashReadID" which
will fetch and return JEDEC ID. This JEDEC ID can be then printed
along with the NOR Flash info by NorFlashInfoLib. If this functionality
is not needed then the function can just return EFI_UNSUPPORTED.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch adds error_handler1 and error_handler2 labels in
NorFlashCreateInstance() function to handle the cleanup.
error_handler1: Frees just the Instance structure as the
ShadowBuffer is not allocated yet.
error_handler2: Frees both Instance and Instance->ShadowBuffer.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This variable holds the QSPI controller's base address.
It is defined in ARM.dec as well with the default value of 0x0.
In case a platform is not using it, they can just ignore this
variable and the default value of 0x0 will be propogated and
the variable will not be used.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch adds the following major changes:
1. Adds changes in NorFlashDxe to look for NorFlashDeviceLib instead of
NorFlash.c for flash specific implementation
2. Remove NorFlash.c and NorFlash.h as they are no longer required.
3. Add changes to platform description files to provide
P30NorFlashDeviceLib as NorFlashDeviceLib
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch implements functions to interact with P30 NOR Flash.
The code is taken from Platform/ARM/Drivers/NorFlashDxe/NorFlash.c
file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch splits NorFlash.h and moves out the function prototypes and
macros that are expected by NorFlashDxe to be implemented by any
Nor Flash implementation to NorFlashDeviceLib.h file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch makes local functions not being used outside
NorFlash.c STATIC.
Also, NorFlashWriteBuffer() is specific to a particular
flash implementation and need not be implemented by
other NOR flash device IPs.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch removes NorFlashReadCfiData() and NorFlashWrite()
prototypes from NorFlash.h as these are not implemented or
used anywhere in NorFlashDxe driver.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Refactoring done in this patch has two major parts:
1. Moving out NorFlashUnlockAndEraseSingleBlock and
NorFlashWriteFullBlock functions from NorFlashDxe.c and
NorFlashStandaloneMm.c to NorFlash.c files.
2. At the same time, we are adding NorFlashLock and NorFlashUnlock
functions which will take care of TPL related operations needed by
functions mentioned in point 1. These functions are implemented
in NorFlashDxe.c but are just dummy placeholder functions in
NorFlashStandaloneMm.c file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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This patch splits NorFlash.h and adds NorFlashCommon.h which
will have all the flash independent functions and macros.
Whereas all the flash specific functions will be in NorFlash.h
header file.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Moving this function from NorFlash.c to NorFlashDxe.c as it is not
dependent on any particular flash implementation.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Moving these functions from NorFlash.c to NorFlashBlockIoDxe.c as
they are not dependent on any particular flash implementation.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Remove CTA15-A7 support, its associated libraries and files.
This effort was started by:
https://edk2.groups.io/g/devel/message/115378
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Remove CTA15-A7 platform support. This effort was started by:
https://edk2.groups.io/g/devel/message/115378
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The ArmVExpressLibSec is not used anymore. The library is defined
for the ArmVExpress-FVP-AArch64.dsc platform, but is not actually
used.
Remove the library.
This motivation of this patch is also to remove the unique
reference to ArmCortexA9.h file:
https://edk2.groups.io/g/devel/message/115378
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set the
desired performance. In addition to this, RD-Fremont platform does not
support CPPC revision 1 and below. So update the _OSC method to let OSPM
know about this fact.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file as well to define the PCDs for its generation of
platforms.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
adding support for this platform, add the initial set of ACPI tables and
reuse existing ACPI tables as applicable to boot a operating system on
this platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective <platform>.dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD to 64-bit.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as defined
by the ACPI 6.x specification. There is a typo in the macro definition
where the 'fastchannel address of the performance limited register' is
mentioned instead of the 'performance limited register address'.
Correcting this typo. However, it's important to retain the reference to
the performance limited register in the macro for future use, as it will
prove useful once functionalities such as power metering devices are
enabled.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The Neoverse RD-N2-Cfg3 platform is a variant of RD-N2 platform with a
different mesh size and GIC ITS count. As part of the initial platform
support, add the corresponding platform and flash description files.
Use PcdPlatformVariant for the RD-N2-Cfg3 platform to specify the
platform variant. RD-N2-Cfg3 has 12 GIC ITS blocks when compared to the
other RD-N2 variants that have 6 GIC ITS blocks.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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A new PCD named PcdPlatformVariant is introduced to specify the variant
number of a platform. This PCD can be used to select platform variant
specific configurations. The default value of this PCD is 0 which
selects the base variant.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3479
A recent change in MdeModulePkg [1] introduced VariableFlashInfoLib as a
dependency to support dynamic variable flash information. Add an
instance for the library class VariableFlashInfoLib in
SgiPlatformMm.dsc.inc to resolve this dependency.
[1]: https://github.com/tianocore/edk2/commit/8db39c60cdf35e0a53ccdbccf7e152ab41f54f4c
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The software executing at a higher privileged level on the reference
design platforms have been updated to allow software executing at EL1
and EL0 to access the Advanced SIMD and floating-point registers (FPEN
field of CPACR_EL1 system register is programmed to allow access). So,
remove the use of +nofp gcc build option flag.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Add Standalone MM support for FVP model.
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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UEFI Secure variable support can be enabled using Standalone MM
for FVP RevC model.
The following steps enable UEFI variable service using StandaloneMm:
1. Add MmComminucationDxe.
- Enables communication with StandaloneMm.
The PcdMmBufferBase & PcdBufferSize definitions are used
as the NS Shared Buffer for communication.
2. Use VariableSmmRuntimeDxe
- Use Standalone MM instance of Variable Runtime Dxe.
3. Disable caching of variable data as this is cached on the
normal world side. This is done to prevent arbitrary accesses.
Therefore, set PcdEnableVariableRuntimeCache to FALSE.
4. Although MmUnblockMemoryLib is required for supporting variable
caching (which we disabled), we need a NULL instance of the
MmUnblockMemoryLib for the build to succeed.
Also, the Arm implementation does not support modification of
the StandaloneMm memory map from normal world, so we have no
real need for MmUnblockMemoryLib.
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The NOR Flash1 is used for UEFI Variable storage. When
Standalone MM is enabled the variable storage is managed
in the secure world by Standalone MM.
Therefore, add a new instance of NorFlashLib for that has
the NOR Flash1 definitions for Standalone MM.
Also, disable the NOR Flash1 definitions from the Normal
world NorFlashLib instance when Standalone MM is enabled
using the ENABLE_STMM build flag.
Signed-off-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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N1SdpNtFwConfigPei PEIM extracts platform information from NT_FW_CONFIG
and provides it to other modules as a PPI and a HOB.
Therefore, update ConfigurationManagerDxe to consume these values from
the HOB in the DXE phase.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Incorporate N1SdpNtFwConfigPei PEI module which parses NT_FW_CONFIG and
passes it to other PEI modules(as PPI) and DXE modules(as HOB).
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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Update the RegisterBase and Clk for the Debug Serial Port (DBG2)
to route it to the IOFPGA UART1 and make the SPCR and DBG2 Serial
Ports exclusive.
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The SsdtCpuTopologyGenerator can generate _CPC objects.
This is done by querying the SCP for the relevant performance
state information through SCMI. CM_ARM_CPC_INFO are then populated
and used to generate _CPC objects in the Ssdt Cpu topology.
Use the DynamicTablesScmiInfoLib and add the handling to generate
_CPC information.
Note that using _CPC is only possible if SCP is correctly tuned
to advertise performance levels on an abstract and unified scale.
A basic check is done to prevent the _CPC generation otherwise.
Perf level values used for testing:
- little CPUs OPPs: [181, 322, 383] * 1000
- big CPUs OPPs: [512, 833, 1024] * 1000
Also make use of the newly added PcdDevelopmentPlatformRelaxations
and add a new ENABLE_CPC build parameter ('-D ENABLE_CPC') to enable
CPC generation.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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The SsdtCpuTopologyGenerator can generate _PSD objects.
Add _PSD information and handling to the Configuration Manager
to generate them.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Fix a typo.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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The edk2 commit 7284c44951cffd52f1a08367d91b5c63c7bb9c16
introduces a new library ImagePropertiesRecordLib to
consolidate the logic for manipulating the image properties
used to track runtime images and to remove duplicate code.
This library is further linked with DxeCore.
Therefore, add an instance of ImagePropertiesRecordLib to
the ArmVExpress.dsc.inc file so that it is included for Arm
platforms.
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Tested-by: Pierre Gondois <pierre.gondois@arm.com>
Tested-by: Nuno Lopes <Nuno.Lopes@arm.com>
Tested-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
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ImagePropertiesRecordLib is used by DxeMain and PiSmmCore, so it
needs to be added to most platforms.
Signed-off-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
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When ETE is enabled in the FVP model the firmware can check
the debug feature register ID_AA64DFR0_EL1.TraceVer field
to identify the presence of FEAT_ETE and add an ETE device
to the CPU node in the AML CPU hierarchy. This enables the
Operating System driver to probe and enable ETE support.
Note: To enable ETE support in the FVP REvC model
1. Build TF-A with the CTX_INCLUDE_AARCH32_REGS=0
build flag set, otherwise this results in an
exception when booting TF-A
2. Set the model parameters to enable TRBE as this
is required for ETE
-C cluster0.has_trbe=1 -C cluster1.has_trbe=1
3. Set the ETE plugin for the model
--plugin <PLUGIN_PATH>\libete-plugin.[so|dll]
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
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