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<title>Tianocore/edk2-platforms.git/Silicon/Socionext, branch CodeCleanup</title>
<subtitle>EDK II sample platform branches and tags (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup</id>
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<updated>2023-11-22T15:12:53+00:00</updated>
<entry>
<title>multiple Arm platforms: set WritePolicyValid for all cache types</title>
<updated>2023-11-22T15:12:53+00:00</updated>
<author>
<name>Marcin Juszkiewicz</name>
<email>marcin.juszkiewicz@linaro.org</email>
</author>
<published>2023-11-15T12:46:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=10e2eb030de3fa96433009465aab6eff0f199117'/>
<id>urn:sha1:10e2eb030de3fa96433009465aab6eff0f199117</id>
<content type='text'>
acpiview complains:

ERROR: On Arm based systems, all cache properties must be provided in
the cache type structure. Missing 'Write Policy Valid' flag.

ACPI specification says:

&gt; Set to 1 if the write policy attribute described is valid. A value
&gt; of 0 indicates that, where possible, processor architecture specific
&gt; discovery mechanisms should be used to ascertain the value of this
&gt; attribute.

Signed-off-by: Marcin Juszkiewicz &lt;marcin.juszkiewicz@linaro.org&gt;
Reviewed-by: Leif Lindholm &lt;quic_llindhol@quicinc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/SynQuacer: Drop dependency on NorFlashPlatformLib</title>
<updated>2022-10-19T14:51:15+00:00</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2022-10-19T11:49:06+00:00</published>
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<id>urn:sha1:85280b124e5adc8713050d9a3ec14228735a48b9</id>
<content type='text'>
Fip006Dxe is part of the SynQuacer platform, which is its only user, and
yet, it relies on NorFlashPlatformLib to carry the platform specific NOR
geometry. This library is tied to ArmPlatformPkg's NorFlashDxe, which
will be going away, so let's stop using it.

Since the abstraction serves no purpose here, let's just merge the
library with its only user.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Reviewed-by: Leif Lindholm &lt;quic_llindhol@quicinc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/SynQuacer/PlatformDxe: set ACPI as default hardware description</title>
<updated>2022-08-19T08:10:38+00:00</updated>
<author>
<name>Masahisa Kojima</name>
<email>masahisa.kojima@linaro.org</email>
</author>
<published>2022-08-19T07:00:14+00:00</published>
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<id>urn:sha1:46686eeb7e78efe603badd86f13777d9fb070fb8</id>
<content type='text'>
Since ACPI is well supported on SynQuacer platform, set ACPI as
default hardware description.

Only changing the "DEFAULT" flags from ACPIPREF_DT to ACPIPREF_ACPI
does not work as expected, this commit also replaces the value
of ACPIPREF_DT and ACPIPREF_ACPI.

Signed-off-by: Masahisa Kojima &lt;masahisa.kojima@linaro.org&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Silicon/Socionext/SynQuacer: Update for IORT revision macro renaming</title>
<updated>2022-07-29T18:38:27+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2022-07-14T16:55:24+00:00</published>
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<id>urn:sha1:d5cabcfb6b335b3b221d09121e737f158134703d</id>
<content type='text'>
The IORT Specification E.d updates the IORT table revision to 5. To
reflect this change the IORT header file has been updated to rename
the EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro which was at Rev 0 to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Therefore, update the usage of EFI_ACPI_IO_REMAPPING_TABLE_REVISION
macro in the IORT table for SynQuacer platform to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Silicon/SynQuacer: add DBG2 ACPI table</title>
<updated>2022-07-22T16:53:35+00:00</updated>
<author>
<name>Masami Hiramatsu</name>
<email>masami.hiramatsu@linaro.org</email>
</author>
<published>2021-12-10T06:51:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=86759a1bf82904fec4ce5abe3bb7c04948822767'/>
<id>urn:sha1:86759a1bf82904fec4ce5abe3bb7c04948822767</id>
<content type='text'>
Add DBG2 table to ACPI tables. The COM1 uart port will be used
for OS debug, and it is 16550 compatible.

Signed-off-by: Masami Hiramatsu &lt;masami.hiramatsu@linaro.org&gt;
</content>
</entry>
<entry>
<title>Silicon/SynQuacer/Fip006Dxe: Support 4-bytes address for erase and write</title>
<updated>2022-05-16T14:09:23+00:00</updated>
<author>
<name>Kazuhiko Sakamoto</name>
<email>sakamoto.kazuhiko@socionext.com</email>
</author>
<published>2022-05-10T08:25:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=03d1c51272c053c0b7ef8d3a16fabd26d7c51d8c'/>
<id>urn:sha1:03d1c51272c053c0b7ef8d3a16fabd26d7c51d8c</id>
<content type='text'>
Support 4-bytes address for erase and write, so that we can
access whole region of SPI-NOR Flash(64MiB) implemented on the
Developerbox.

This commit also fixes the wrong macro name. SPINOR_OP_SE and
SPINOR_OP_SE_4B is the commoand for 64KB block erase,
it must be SPINOR_OP_BE and SPINOR_OP_BE_4B.

Signed-off-by: Masahisa Kojima &lt;masahisa.kojima@linaro.org&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Silicon/Socionext: Update ARM_CORE_INFO initializer for MPIDR field change</title>
<updated>2022-01-30T10:25:32+00:00</updated>
<author>
<name>Rebecca Cran</name>
<email>rebecca@nuviainc.com</email>
</author>
<published>2021-12-16T22:07:50+00:00</published>
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<id>urn:sha1:afdc12556108646c0e0449d710dac2f519d671b5</id>
<content type='text'>
The ARM_CORE_INFO struct has been updated so the MPIDR is now a single
field instead of separate cluster/core fields. Update the initializer.

Signed-off-by: Rebecca Cran &lt;rebecca@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Platform/Socionext/DeveloperBox: add SMBIOS type 17 table</title>
<updated>2021-12-02T07:50:53+00:00</updated>
<author>
<name>Masahisa Kojima</name>
<email>masahisa.kojima@linaro.org</email>
</author>
<published>2021-11-30T08:41:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=c718abce99a1c20578d62486ca7f3864643059a0'/>
<id>urn:sha1:c718abce99a1c20578d62486ca7f3864643059a0</id>
<content type='text'>
This commit adds the SMBIOS type 17 table support for Developerbox.
The SPD can be accessed only from the SCP through I2C bus,
so this commit expects that SCP-firmware reads the SPD and
stores it in the non-secure SRAM.

This commit also reduces the edk2 stack size to allocate
the space for storing SPD. It requires 2KB, 512bytes * 4 DIMMs.

Cc: Leif Lindholm &lt;leif@nuviainc.com&gt;
Cc: Masami Hiramatsu &lt;masami.hiramatsu@linaro.org&gt;
Signed-off-by: Masahisa Kojima &lt;masahisa.kojima@linaro.org&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Silicon/Socionext: fix line endings</title>
<updated>2021-11-26T17:31:11+00:00</updated>
<author>
<name>Leif Lindholm</name>
<email>leif@nuviainc.com</email>
</author>
<published>2021-11-11T11:41:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=3e73df15730667c46a1e449cca872e7f8861007c'/>
<id>urn:sha1:3e73df15730667c46a1e449cca872e7f8861007c</id>
<content type='text'>
SynQuacerI2cDxe.c (and no other Socionext source files) has LF instead of
CRLF line endings, so fix that.

Signed-off-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
Cc: Masami Hiramatsu &lt;masami.hiramatsu@linaro.org&gt;
Acked-by: Ard BIesheuvel &lt;ardb@kernel.org&gt;
Acked-by: Masami Hiramatsu &lt;masami.hiramatsu@linaro.org&gt;
</content>
</entry>
<entry>
<title>Silicon/SynQuacerI2cDxe: Test the ControllerHandle is managed by this driver</title>
<updated>2021-10-29T17:14:10+00:00</updated>
<author>
<name>Kazuhiko Sakamoto</name>
<email>sakamoto.kazuhiko@socionext.com</email>
</author>
<published>2021-10-13T05:36:59+00:00</published>
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<id>urn:sha1:d38eafe2321d18e3d4470b64381b5ba76f4c5f35</id>
<content type='text'>
Test the @ControllerHandle is not NULL and is actually managed by
this driver.

Signed-off-by: Masami Hiramatsu &lt;masami.hiramatsu@linaro.org&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
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