Tianocore/edk2-platforms.git/Silicon/RISC-V, branch CodeCleanup

Silicon/RiscVOpensbiLib: fix submodule version

2024-07-04T11:14:46+00:00

Commit 4f32c34865de, ("Platform/AMD: Initial commit of cross platform/board interfaces") presumably by accident reverts the opensbi submodule update done in commmit 2d8289634ec9 ("ProcessorPkg/opensbi: Update opensbi library"). Correct this and restore the submodule version. Cc: Daniel Schaefer Cc: Sunil V L Cc: Abner Chang Signed-off-by: Leif Lindholm Reviewed-by: Sunil V L

Platform/AMD: Initial commit of cross platform/board interfaces

2024-05-24T05:06:48+00:00

BZ#: 4777 Initial commit of AMD cross platform/board generic encapsulated software architecture. This provides the basic definitions and protocols for the follow-up AMD open board project. Cc: Paul Grimes Cc: Abdul Lateef Attar Cc: Igniculus Fu Cc: Ken Yao Cc: Eric Xing Cc: Duke Zhai Signed-off-by: Abner Chang Reviewed-by: Eric Xing Reviewed-by: Ken Yao Reviewed-by: Duke Zhai Reviewed-by: Paul Grimes < paul.grimes@amd.com> Reviewed-by: Abdul Lateef Attar

Silicon/RISC-V: remove redundant function code from RiscVCpuLib

2023-04-17T10:18:55+00:00

They had been implemented in MdePkg/Library/BaseLib Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai Reviewed-by: Sunil V L

Silicon/RISC-V: remove redundant RiscVTimerLib

2023-04-17T10:18:55+00:00

It will be replaced by UefiCpuPkg/Library/BaseRiscV64CpuTimerLib. Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai Reviewed-by: Sunil V L

Silicon/RISC-V/ProcessorPkg: remove redundant CpuDxe driver

2023-04-17T10:18:55+00:00

UefiCpuPkg/CpuDxeRiscV64 will replace it later. Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai Reviewed-by: Sunil V L

RISC-V/RiscVExceptionLib: Follow new CpuExceptionHandlerLib APIs

2022-08-22T08:01:03+00:00

CpuExceptionHandlerLib (in EDK2) has been refactored with following changes 1. Removed InitializeCpuInterruptHandlers in 2a09527ebcb459b40 2. Removed InitializeCpuExceptionHandlersEx and added InitializeSeparateExceptionStacks in e7abb94d1fb8a0e7 The patch updates RISC-V version of CpuExceptionHandlerLib to follow the API changes, based on the ARM changes in e2ae0bed29ca0900bd35. The functionality to RISC-V platforms should be none. Signed-off-by: Daniel Schaefer Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI Uncrustify errors

2022-02-18T06:10:30+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI Spelling errors.

2022-02-18T06:10:29+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI library header check errors

2022-02-18T06:10:29+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI ECC errors.

2022-02-18T06:10:29+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L