Tianocore/edk2-platforms.git/Silicon/RISC-V/ProcessorPkg/Include, branch CodeCleanup

Silicon/RISC-V: remove redundant function code from RiscVCpuLib

2023-04-17T10:18:55+00:00

They had been implemented in MdePkg/Library/BaseLib Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Evan Chai Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI Uncrustify errors

2022-02-18T06:10:30+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI Spelling errors.

2022-02-18T06:10:29+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L

RISC-V/ProcessorPkg: Address Core CI ECC errors.

2022-02-18T06:10:29+00:00

Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L Reviewed-by: Sunil V L

RiscV/ProcessorPkg: Create read mtime CSR library instances

2021-11-10T06:57:43+00:00

Create library instances of reading Machine mode timer. - MacineModeTimerLib is used to read mtime CSR through platfrom library. - EmulatedMacineModeTimerLib is used to read mtime CSR through shadow CSR. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L

RISC-V: Use RISC-V PeiCoreEntryPoint library

2021-11-10T06:50:01+00:00

1. Use RISC-V PeiCoreEntryPoint library instance for opensbi to switch to the next phase with arg0 as HART Id and arg1 as the SEC to PEI handoff data. 2. Introduce EDK2 opensbi platform operation functions. With this, OEM can has its won platform initialization code before and/or after opensbi vendor platform functions. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Reviewed-by: Sunil V L

RISC-V: Implement ResetSystem RT call

2021-10-19T04:17:25+00:00

Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer

RISC-V: Switch to latest OpenSBI

2021-10-19T04:17:24+00:00

Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer

RISC-V/PlatformPkg: Build DeviceTree and use that in SEC

2021-10-19T04:17:23+00:00

OpenSBI uses the device tree for platform specific initialization, so we need to have it already in SEC. Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer

Silicon/RISC-V: Introduce FirmwareContext library

2021-10-19T04:17:21+00:00

Add RISC-V FirmwareContext library for different FirmwareContext implementations. This instance uses SBI firmware extension to get the pointer to FirmwareContext. Cc: Sunil V L Cc: Daniel Schaefer Reviewed-by: Abner Chang Reviewed-by: Daniel Schaefer Signed-off-by: Abner Chang