Tianocore/edk2-platforms.git/Silicon/NXP/Library, branch CodeCleanup

NXP/Pcf8563RealTimeClockLib: hide LibRtcVirtualNotifyEvent

2023-10-13T10:12:01+00:00

The RealTimeClockLib class header in edk2 mistakenly declares a function called LibRtcVirtualNotifyEvent(). No component ever calls this function crossing module boundaries; all RealTimeClockLib instances in edk2 and edk2-platforms are supposed to register (and do register) their SetVirtualAddressMap() notification functions. Rename LibRtcVirtualNotifyEvent() to VirtualNotifyEvent(), and make it static, in preparation for removing the LibRtcVirtualNotifyEvent() declaration from the lib class header later. Build-tested only (with "DeveloperBox.dsc"). Cc: Leif Lindholm Cc: Masami Hiramatsu Cc: Meenakshi Aggarwal Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4564 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel

Silicon/NXP/Pcf8563RealTimeClockLib: Clear Nanosecond field in GetTime

2021-07-28T10:43:43+00:00

Clear unsupported Nanosecond field of the EFI_TIME data structure. Without this fix, date/time commands on UEFI shell fail to set because of the invaild parameter error. This is tested on the SynQuacer DeveloperBox platform which also uses 'Pcf8563' RTC chip. Signed-off-by: Masami Hiramatsu Reported-by: Kazuhiko Sakamoto

Silicon/NXP: Add GPIO Library support.

2020-10-09T16:02:29+00:00

General-purpose I/O (GPIO) module is integrated on chip. In general, the GPIO module supports up to 32 general-purpose I/O ports. Each port can be configured as an input or as an output. However, some implementations may restrict specific ports to input-only, output-only, or reserved (unimplemented). Co-authored-by: Pramod Kumar Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm

Platform/NXP: LX2160aRdbPkg: Hide Root Port for LX2160A-Rev2

2020-07-03T14:43:25+00:00

PCIe Layerscape controller in LX2160A-Rev2 is not completely ECAM-compliant. It is non-ECAM only for the root bus (bus 0) and for any other bus underneath the root bus it does support ECAM access. One approach can be to setup the controller in firmware and expose bus[0x1-0xff] to OS via MCFG and DSDT table. Introduce PcdPciHideRootPort PCD and set it for LX2160A-Rev2 for this. Limit the size of CFG0 iATU window (for type0 config transactions) to 32KB to avoid enumuration of unwanted devices in OS. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP: SerDesHelperLib: Correct DEBUG log

2020-06-17T12:32:38+00:00

Update DEBUG log to indicate SerDes protocol is in hex. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers

2020-06-12T15:31:36+00:00

Based on the serdes protocol value in reset configuration word (RCW), different PCIe controllers are enabled. Get SerDes protocol map and initialize only enabled PCIe controllers. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP/Library: Implement SerDesHelperLib

2020-06-12T15:31:20+00:00

Implement SerDesHelperLib to provide helper functions which can be used for SoC specific SerDes configuration. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP: Implement PL011UartClockLib for NXP platforms

2020-06-01T17:58:31+00:00

In NXP SOCs the UART clock is derived from System clock after PLL multiplication. Therefore, add the PL011UartClockLib implementation for NXP platforms. Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm

Silicon/NXP/PciHostBridgeLib: Fix compilation with MDEPKG_NDEBUG flag

2020-06-01T17:58:16+00:00

when MDEPKG_NDEBUG flag is enabled, RELEASE build fails with this error: error: mPciHostBridgeLibAcpiAddressSpaceTypeStr defined but not used [-Werror=unused-variable] Fix this error by protecting mPciHostBridgeLibAcpiAddressSpaceTypeStr with MDEPKG_NDEBUG macro. Suggested-by: Leif Lindholm Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm

Silicon/NXP: PciSegmentLib: LsGen4Ctrl: Add Workaround for A-011264

2020-05-26T09:48:59+00:00

With PCIe LsGen4 controller, clearing the Bus Master Enable bit in Command register blocks all outbound transactions to be sent out in RC mode. According to PCI Express base specification, the Command register's Bus Master Enable bit of a PCI Express RC controller can only control the forwarding of memory requests received at its root port in the upstream direction. In other words, clearing the Bus Master Enable bit must not block all outbound transactions to be sent out toward RC's downstream devices. Due to this erratum, when the Command register's Bus Master Enable bit is cleared, all the outbound transactions from the device's internal bus masters, including but not limited to configuration read and write transactions, are terminated with the slave error (SLVERR) response status on the PCI Express RC controller's internal AXI bus interface. Signed-off-by: Wasim Khan Reviewed-by: Ard Biesheuvel