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<title>Tianocore/edk2-platforms.git/Silicon/NXP/Library/MemoryInitPeiLib, branch CodeCleanup</title>
<subtitle>EDK II sample platform branches and tags (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup'/>
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<updated>2020-05-15T21:26:42+00:00</updated>
<entry>
<title>Platform/NXP/LS1043aRdbPkg: Add PEI Phase</title>
<updated>2020-05-15T21:26:42+00:00</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2020-05-01T05:49:55+00:00</published>
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<id>urn:sha1:459cfc6bd38e29c52866aa68f9d8ff8c1e82154f</id>
<content type='text'>
Add PEI phase to LS1043aRdb. This is needed because we need to have
dynamic PCDs support to be able to reserve memory before reporting
memory to UEFI firmware.
Using PEI phase we are now also dynamically setting the
PcdSystemMemoryBase and PcdSystemMemorySize depending upon the DRAM
regions detected.
This in turn would depend on the DDR DIMMs installed on board.

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP: move MemoryInitPeiLib as per PEIM structures</title>
<updated>2020-05-15T21:26:38+00:00</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2020-05-01T05:49:54+00:00</published>
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<id>urn:sha1:9ca0d3c8fde9308cdc5971cd48ffb098647453ab</id>
<content type='text'>
MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement
PEI phase. therefore, move the library to directory of same name.

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
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