Tianocore/edk2-platforms.git/Silicon/NXP/Include, branch CodeCleanup

Silicon/NXP: Implement USB Errata Workarounds

2020-10-09T16:02:48+00:00

Implement workarounds for USB errata A008997, A009007, A009008, A009798 for chassis2 Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm

Silicon/NXP: Add SCFG support for Chassis2

2020-10-09T16:02:42+00:00

Add support for SCFG (Supplemental Configuration Unit) register space and helper functions to R/W SCFG registers Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm

Silicon/NXP: Add GPIO Library support.

2020-10-09T16:02:29+00:00

General-purpose I/O (GPIO) module is integrated on chip. In general, the GPIO module supports up to 32 general-purpose I/O ports. Each port can be configured as an input or as an output. However, some implementations may restrict specific ports to input-only, output-only, or reserved (unimplemented). Co-authored-by: Pramod Kumar Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm

Platform/NXP: LX2160aRdbPkg: Hide Root Port for LX2160A-Rev2

2020-07-03T14:43:25+00:00

PCIe Layerscape controller in LX2160A-Rev2 is not completely ECAM-compliant. It is non-ECAM only for the root bus (bus 0) and for any other bus underneath the root bus it does support ECAM access. One approach can be to setup the controller in firmware and expose bus[0x1-0xff] to OS via MCFG and DSDT table. Introduce PcdPciHideRootPort PCD and set it for LX2160A-Rev2 for this. Limit the size of CFG0 iATU window (for type0 config transactions) to 32KB to avoid enumuration of unwanted devices in OS. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP: LS1043A: Add SocGetSvr API

2020-06-18T15:27:06+00:00

Add SocGetSvr API to get the System Version Register(SVR) Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP: LS1043A: Add SerDes Support

2020-06-12T15:31:29+00:00

Based on SerDes protocol value in reset configuration word (RCW) different IP blocks gets enabled in HW. Add SoC specific SerDes configuration for LS1043A, which can be used by different IPs to know the enabled interfaces and perform the required initialization. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP/Library: Implement SerDesHelperLib

2020-06-12T15:31:20+00:00

Implement SerDesHelperLib to provide helper functions which can be used for SoC specific SerDes configuration. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm

Silicon/NXP/Drivers: Implement PciCpuIo2Dxe Driver

2020-05-26T09:48:59+00:00

NXP SoC has multiple PCIe RCs and there is no fix translation offset between I/O port accesses and MMIO accesses. Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL to add the translation for different RCs for IO access. Signed-off-by: Wasim Khan Reviewed-by: Ard Biesheuvel

Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451

2020-05-26T09:33:02+00:00

When PCIe Layerscape Gen4 controller is sending multiple split completions and ACK latency expires indicating that ACK should be send at priority. But because of large number of split completions and FC update DLLP,the controller does not give priority to ACK transmission. This results into ACK latency timer timeout error at the link partner and the pending TLPs are replayed by the link partner again. Workaround: Reduce the ACK latency timeout value. Co-authored-by: Vabhav Sharma Co-authored-by: Wasim Khan Signed-off-by: Wasim Khan Reviewed-by: Ard Biesheuvel

Silicon/NXP: PciHostBridgeLib: Setup PCIe LsGen4 Controller and ATU Windows

2020-05-26T09:33:02+00:00

Setup PCIe LayerscapeGen4 controller and setup CFG, IO, MMIO and MMIO64 iATU windows. Check for PcdPciLsGen4Ctrl to enable LsGen4 PCIe controller. Co-authored-by: Vabhav Sharma Co-authored-by: Wasim Khan Signed-off-by: Wasim Khan Reviewed-by: Ard Biesheuvel