<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2-platforms.git/Silicon/NXP/Include/Library, branch CodeCleanup</title>
<subtitle>EDK II sample platform branches and tags (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/'/>
<updated>2020-10-09T16:02:48+00:00</updated>
<entry>
<title>Silicon/NXP: Implement USB Errata Workarounds</title>
<updated>2020-10-09T16:02:48+00:00</updated>
<author>
<name>Meenakshi Aggarwal</name>
<email>meenakshi.aggarwal@oss.nxp.com</email>
</author>
<published>2020-10-09T15:19:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=ae7ee12a0379dcfe0738364edb71fa499c58bb12'/>
<id>urn:sha1:ae7ee12a0379dcfe0738364edb71fa499c58bb12</id>
<content type='text'>
Implement workarounds for USB errata A008997, A009007,
A009008, A009798 for chassis2

Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP: Add SCFG support for Chassis2</title>
<updated>2020-10-09T16:02:42+00:00</updated>
<author>
<name>Meenakshi Aggarwal</name>
<email>meenakshi.aggarwal@oss.nxp.com</email>
</author>
<published>2020-10-07T16:10:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=ddcb92cc5d5c77120769687cd376449512e87abd'/>
<id>urn:sha1:ddcb92cc5d5c77120769687cd376449512e87abd</id>
<content type='text'>
Add support for SCFG (Supplemental Configuration Unit)
register space and helper functions to R/W SCFG registers

Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP: Add GPIO Library support.</title>
<updated>2020-10-09T16:02:29+00:00</updated>
<author>
<name>Meenakshi Aggarwal</name>
<email>meenakshi.aggarwal@oss.nxp.com</email>
</author>
<published>2020-10-07T16:10:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=f4b89f521115b5a9d8d085f98df74eb302653798'/>
<id>urn:sha1:f4b89f521115b5a9d8d085f98df74eb302653798</id>
<content type='text'>
General-purpose I/O (GPIO) module is integrated on chip.

In general, the GPIO module supports up to 32 general-purpose
I/O ports. Each port can be configured as an input or as an
output. However, some implementations may restrict specific ports to
input-only, output-only, or reserved (unimplemented).

Co-authored-by: Pramod Kumar &lt;pramod.kumar_1@nxp.com&gt;
Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP: LS1043A: Add SocGetSvr API</title>
<updated>2020-06-18T15:27:06+00:00</updated>
<author>
<name>Wasim Khan</name>
<email>wasim.khan@nxp.com</email>
</author>
<published>2020-06-09T21:20:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=68dd864ca1a6e6df9d4c33e70994901a4d0a8c0d'/>
<id>urn:sha1:68dd864ca1a6e6df9d4c33e70994901a4d0a8c0d</id>
<content type='text'>
Add SocGetSvr API to get the System Version Register(SVR)

Signed-off-by: Wasim Khan &lt;wasim.khan@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP: LS1043A: Add SerDes Support</title>
<updated>2020-06-12T15:31:29+00:00</updated>
<author>
<name>Wasim Khan</name>
<email>wasim.khan@nxp.com</email>
</author>
<published>2020-06-08T18:52:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=78e9f8a129c326f4a329709bc62c69ae299f4f3a'/>
<id>urn:sha1:78e9f8a129c326f4a329709bc62c69ae299f4f3a</id>
<content type='text'>
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LS1043A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.

Signed-off-by: Wasim Khan &lt;wasim.khan@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP/Library: Implement SerDesHelperLib</title>
<updated>2020-06-12T15:31:20+00:00</updated>
<author>
<name>Wasim Khan</name>
<email>wasim.khan@nxp.com</email>
</author>
<published>2020-06-08T18:52:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=7bdb08fa3c08d434b2c999ee1d319dd2515a13f8'/>
<id>urn:sha1:7bdb08fa3c08d434b2c999ee1d319dd2515a13f8</id>
<content type='text'>
Implement SerDesHelperLib to provide helper functions which
can be used for SoC specific SerDes configuration.

Signed-off-by: Wasim Khan &lt;wasim.khan@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit</title>
<updated>2020-05-15T21:26:20+00:00</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2020-05-01T05:49:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=b7d1d0813f0a80c3a31bee5d2c76cfda7a135267'/>
<id>urn:sha1:b7d1d0813f0a80c3a31bee5d2c76cfda7a135267</id>
<content type='text'>
SocInit can be defined in SocLib.h
No need to make it extern in ArmPlatformLib

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon/NXP: Add Chassis2 Package</title>
<updated>2020-05-15T21:25:57+00:00</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2020-05-01T05:49:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=34c93f82b385f9948a0ee63c07aec54a4b339fc1'/>
<id>urn:sha1:34c93f82b385f9948a0ee63c07aec54a4b339fc1</id>
<content type='text'>
A Chassis is a base framework used for building SoCs.
We can think of Chassis/Soc/Platform(a.k.a Board) in Object model terms.
Chassis is base. Soc is based on some Chassis.
Platform is based on some Soc.

SOCs that are designed around same chassis, reuse most of the components.

Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong
to Chassis2.

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Silicon: NXP: Remove direct calls to SwapMmio* APIs</title>
<updated>2020-05-15T21:25:46+00:00</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2020-05-01T05:49:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=d6c774c2faa571caad9ecd6e1cf441346e3495ad'/>
<id>urn:sha1:d6c774c2faa571caad9ecd6e1cf441346e3495ad</id>
<content type='text'>
The SwapMmio** APIs are supposed to be called indirectly via
GetMmioOperations** APIs.
Therefore, remove the SwapMmio** APIs from IoAccessLib.h and make
these APIs STATIC to IoAccessLib.c, so that no accidental call can
be made to these.

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
<entry>
<title>Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs</title>
<updated>2020-05-15T21:25:38+00:00</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2020-05-01T05:49:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=7939fe738f20222a708f79dbe15e3829398ef257'/>
<id>urn:sha1:7939fe738f20222a708f79dbe15e3829398ef257</id>
<content type='text'>
The SOC takes primary clocking input from the external signal (a clock
generator on board). The input (frequency) is multiplied using multiple
phase locked loops (PLL) to create a variety of frequencies which can
then be passed to a variety of internal logic, including cores and
peripheral IP modules.

Therefore, move the clock retrieval APIs to Platform Lib.
The Input clock is retrieved from board components in Platform Lib, and
passed on to SOC Lib APIs to get the correct clock for an IP (after PLL
multiplication).

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Leif Lindholm &lt;leif@nuviainc.com&gt;
</content>
</entry>
</feed>
