Tianocore/edk2-platforms.git/Silicon/ARM, branch CodeCleanupEDK II sample platform branches and tags (mirror)https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup2024-05-29T15:45:56+00:00Silicon/ARM/NeoverseN1Soc: NOR flash library for N1Sdp2024-05-29T15:45:56+00:00sahilsahil@arm.com2024-05-29T08:55:14+00:00urn:sha1:5ae8226c594f75678bb90f8fa36f662b7ef63589
Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable storage.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region2024-05-29T15:45:56+00:00sahilsahil@arm.com2024-05-29T08:55:13+00:00urn:sha1:c1a49aa29666dfe6a73a21f5ae03cf85443f7510
Enable SCP QSPI flash region access by adding it in the PlatformLibMem.
This flash is shared between AP core and System Control Processor. The
lower addresses are used to store SCP and AP boot images and higher
addresses will be used for variable storage.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Consume N1SdpNtFwConfigPei supplied data2024-03-04T14:34:44+00:00sahilsahil@arm.com2024-03-01T13:37:51+00:00urn:sha1:74c558fc92059060c115d246698b2dfc30973d68
N1SdpNtFwConfigPei PEIM extracts platform information from NT_FW_CONFIG
and provides it to other modules as a PPI and a HOB. PlatformLibMem
then consumes these values in the form of a PPI during PEI phase.
The previous approach of fetching platform information from a fixed
address is also removed in this patch.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Add N1SdpNtFwConfigPei PEI module2024-03-04T14:32:20+00:00sahilsahil@arm.com2024-01-04T13:16:14+00:00urn:sha1:9c3bc91587e6457980efc53dee22586c6547004c
This patch adds a PEI to parse NT_FW_CONFIG and pass it to
other PEI modules(as PPI) and DXE modules(as HOB).
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Extract NT_FW_CONFIG address passed by TF-A2024-03-04T14:32:06+00:00sahilsahil@arm.com2024-01-04T13:16:13+00:00urn:sha1:1d5880af204498931d95adf587fa4314832733ab
NT_FW_CONFIG DTB contains platform information passed by TF-A boot
stage. This patch enables support to first extract address of
NT_FW_CONFIG and then pass it to other modules as a PPI.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Fix RemoteDdrSize cast2023-05-02T09:37:53+00:00sahilsahil@arm.com2023-05-02T08:32:27+00:00urn:sha1:35a84b1838baacf0d470e76fb68a6ade30413450
RemoteDdrSize calculation wraps around when booting N1Sdp in
multichip mode. Casting it to UINT64 to fix the issue.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Update CCIX PNP ID2022-12-13T13:08:12+00:00sahilsahil@arm.com2022-12-08T12:07:07+00:00urn:sha1:df870c7beaeedbbbc8cc66b42e26977cd00893a5
The PNP ID 0x0A09 used for CCIX host bridge in the current code
is not defined in any specification and is therefore incorrect.
Also, there is no need for a separate ID for CCIX host bridge,
for the following reasons:
1. CCIX doesn't have any host specific requirements/ingredients
as such.
2. CCIX protocol messages flow over regular PCIe.
3. CCIX devices and root ports are natively discovered using the
CCIX DVSEC.
Therefore, reuse PCIe PNP ID for CCIX.
Signed-off-by: sahil <sahil@arm.com>
Acked-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead2022-01-24T16:08:15+00:00Khasim Syed Mohammedkhasim.mohammed@arm.com2022-01-24T15:55:35+00:00urn:sha1:8dbc05c0b640fa68115dd396edce2e2e58c24d01
The patch removes PciExpressLib implementation for N1Sdp as:
a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
instead of PciRead() which makes the PciExpressLib redundant.
b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
and PciLib cannot be used, PciSegmentLib should be used instead as it
supports multiple segments.
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support2022-01-24T16:08:02+00:00Khasim Syed Mohammedkhasim.mohammed@arm.com2022-01-24T15:55:34+00:00urn:sha1:3fb045f534788fdb84446a6cb1ae52083affb616
This patch enables CCIX root complex support by updating
the root complex node info in PciHostBridge library.
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Silicon/ARM/NeoverseN1Soc: Update PCDs to support multiple PCI root ports2022-01-24T16:07:20+00:00Khasim Syed Mohammedkhasim.mohammed@arm.com2022-01-24T15:55:32+00:00urn:sha1:cfde4aae633f7418ed488cef0bc465fefe44da35
PCD entries are updated to remove the hardcoded assignments and to
add support for multiple PCI root ports.
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>