Tianocore/edk2-platforms.git/Silicon/AMD/Styx/Library, branch CodeCleanup

Styx/RealTimeClockLib: hide LibRtcVirtualNotifyEvent

2023-10-13T10:11:53+00:00

The RealTimeClockLib class header in edk2 mistakenly declares a function called LibRtcVirtualNotifyEvent(). No component ever calls this function crossing module boundaries; all RealTimeClockLib instances in edk2 and edk2-platforms are supposed to register (and do register) their SetVirtualAddressMap() notification functions. Rename LibRtcVirtualNotifyEvent() to VirtualNotifyEvent(), and make it static, in preparation for removing the LibRtcVirtualNotifyEvent() declaration from the lib class header later. Also hoist the function definition above the reference. Build-tested only (with "OverdriveBoard.dsc", "CelloBoard.dsc", "Overdrive1000Board.dsc"). Cc: Leif Lindholm Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4564 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel

Silicon/AMD: Update Styx code to work with changes ARM_CORE_INFO struct

2022-01-30T10:27:13+00:00

The ARM_CORE_INFO struct has been updated so the MPIDR is now a single field instead of separate cluster/core fields. Update the Styx code in AcpiPlatformDxe, PlatInitPei and StyxDtbLoaderLib. Signed-off-by: Rebecca Cran

Silicon/Styx: Use PcdPciMmio(32)64Translation PCD from MdePkg

2021-10-15T10:43:25+00:00

Compliant with BZ: #3665 https://bugzilla.tianocore.org/show_bug.cgi?id=3665 PcdPciMmio(32)64Translation PCD is relocated to MdePkg that leveraged by both ARM and RISC-V arch. This patch uses the one from MdePkg instead the one under ArmPkg. Signed-off-by: Abner Chang Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Daniel Schaefer Acked-by: Leif Lindholm

Silicon/AMD: update Styx to use PcdSet*S APIs

2020-11-26T16:20:19+00:00

The non-status reporting PcdSet functions were deprecated and have now been removed. Update Styx code to assert on error status. Cc: Ard Biesheuvel Signed-off-by: Leif Lindholm Acked-by: Ard Biesheuvel

Silicon/AMD/StyxDtbLoaderLib: omit linux,phandle properties

2019-11-28T15:44:22+00:00

The linux,phandle property is a deprecated alias for the phandle property which was standardized long ago, so don't bother emitting it. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm

Silicon/AMD/StyxDtbLoaderLib: use Cortex-A57 IDs instead of generic ARMv8

2019-11-28T15:44:22+00:00

Use the more precise Cortex-A57 based compatible strings to describe the CPUs and the PMUs in the device tree. For compatibility with existing users, leave the current values as fallback aliases. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm

Silicon/AMD/StyxDtbLoaderLib: add description of the cache topology

2019-11-28T15:44:22+00:00

Emit the cache topology into the device tree too when generating the CPU nodes and the cpu-map. Note that the cache geometries are all fixed and thus hardcoded - the only runtime variable aspect is how many L2 nodes to generate (one per detected cluster) Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm

Silicon/AMD/StyxDtbLoaderLib: add interrupt-affinity property to PMU node

2019-11-28T15:44:22+00:00

AMD Seattle uses a range of SPIs to signal PMU events, and this requires a description in the DT which SPI maps to which CPU. This requires us to defer the generation of the PMU node to a point where the CPU phandles have been allocated. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm

Platform/Overdrive: clean up stream ID descriptions in DT

2019-11-28T14:50:17+00:00

Align the DT description of the SMMU topology and stream IDs with the actual routing of the SoC. As with the preceding IORT change, this is mostly a cleanup exercise, but it does actually fix an issue with the CCP crypto accelerator on B1 silicon. Since the CCP shares its SMMU with the second SATA controller, which is only enabled on B1 silicon, we can drop the logic that disables this SMMU on B0 silicon or on platforms that do not expose any SATA ports on the second controller (such as the Cello). Signed-off-by: Ard Biesheuvel Acked-by: Leif Lindholm

Silicon/AMD: Replace BSD License with BSD+Patent License

2019-05-17T21:22:14+00:00

https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney Reviewed-by: Leif Lindholm