EDK II sample platform branches and tags (mirror) https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup 2021-08-22T13:54:45+00:00 2021-08-22T13:54:45+00:00 Jeremy Linton jeremy.linton@arm.com 2021-08-20T04:16:15+00:00 urn:sha1:fc4eb72f881da00a9d5312594633dc6f7b0d409a Since we plan on toggling between XHCI and PCI the PCI root needs to be in its own SSDT. This is all thats needed of UEFI. The SMC conduit is provided directly to the running OS. When the OS detects this PCIe port on a machine without a MCFG it attempts to connect to the SMC conduit. The RPi definition doesn't have any power mgmt, and only provides a description of the root port. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Jared McNeill <jmcneill@invisible.ca> 2021-08-22T13:54:38+00:00 Jeremy Linton jeremy.linton@arm.com 2021-08-20T04:16:14+00:00 urn:sha1:5cf33c71cb42d677ee294b608c30617e31d2a4ff Lets prepare to switch between XHCI and PCI by moving the XHCI definition into its own SSDT. That way we can select it based on the menu settings. The resource producer/consumer flag is also corrected. Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Jared McNeill <jmcneill@invisible.ca> 2021-06-12T20:02:25+00:00 Sunny Wang Sunny.Wang@arm.com 2021-06-07T07:53:37+00:00 urn:sha1:ea709f165df7899d0a9602fc9f65b824baeac490 Changes: 1. Add code to ConfigDxe driver and AcpiTables module to dynamically build either Mini UART or PL011 UART info in ACPI. This also fixes the issue discussed in https://github.com/pftf/RPi4/issues/118. 2. Cleanup by moving duplicate Debug Port 2 table related defines and structures to a newly created header file (RpiDebugPort2Table.h). Testing Done: - Booted to UEFI shell and use acpiview command to check the result of the different UART settings in config.txt (enabling either Mini UART or PL011) and SPCR, DBG2 tables and device BTH0 are dynamically changed as expected. Signed-off-by: Sunny Wang <sunny.wang@arm.com> Reviewed-by: Pete Batard <pete@akeo.ie> Tested-by: Pete Batard <pete@akeo.ie> 2021-02-20T14:37:20+00:00 Jeremy Linton jeremy.linton@arm.com 2021-02-18T18:37:55+00:00 urn:sha1:311ed3c79047e2a7ad001ab94b240ac6558bf06c The primary problem with the RPi's Arasan controller is the lack of a meaningful capabilities register. With just a sdhci-caps _DSD entry we can provide that information. It can then be bound to the Linux sdhci_iproc driver which already hardcodes the remaining controller bugs. Further we have gotten BRCME88C approved as the HID for the newer eMMC2 controller. So lets define an ACPI object to describe it. Of course both devices are sharing an interrupt so we should also indicate that in the table as well. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Pete Batard <pete@akeo.ie> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> 2020-10-12T17:27:52+00:00 Ard Biesheuvel ard.biesheuvel@arm.com 2020-04-21T09:24:17+00:00 urn:sha1:dac891da5cf326d2b4e9aa5adab1d9320b2dd443 Add an IORT table that will limit XHCI DMA to 2 GB, by setting the DMA width to 31 bits. This is needed for Linux/arm64, which can only reliably deal with devices that are unable to perform DMA to the entire 32-bit address range if it can discover their existence early during boot, and this is before the ACPI interpreter is up and running (which rules out calling the _DMA method of the XHC0 object) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> 2020-09-01T12:11:30+00:00 Jeremy Linton jeremy.linton@arm.com 2020-08-31T17:25:47+00:00 urn:sha1:955930dcc5f770260db799f82de0b5f2a30bfdd4 Now that we have a thermal zone we can add active cooling by specifying active cooling points (_ACx) which can be tied to fan objects that turn fans on/off using GPIO pins. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Pete Batard <pete@akeo.ie> 2020-05-12T17:19:35+00:00 Ard Biesheuvel ard.biesheuvel@arm.com 2020-05-12T07:18:02+00:00 urn:sha1:b26c406249e99cf6993abb8af26ec649ef4fe0e8 Move PCDs from GENET driver to Raspberry Pi and Bcm27xx packages. The Genet driver follows the UEFI driver model, so it should not have PCDs defined that describe MMIO and MAC addresses of a single instance. Also, move related definitions around, and update references accordingly. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> 2020-03-26T16:45:22+00:00 Jeremy Linton lintonrjeremy@gmail.com 2020-03-26T16:30:16+00:00 urn:sha1:6beb1692b09b69c02811ee195e7a785d23141b57 ACPI 6.2 adds a new table, which describes how processing units are related to each other in tree like fashion. Caches are also sprinkled throughout the tree and describe the properties of the caches in relation to other caches and processing units. Add a static PPTT table with one L2 cache and an L1I/L1D cache for each of the 4 cores. The cache size/assc/policy/etc are from the public docs. The source from the aslc is derived from the one in: Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> 2020-03-26T12:34:45+00:00 Pete Batard pete@akeo.ie 2020-03-26T11:53:19+00:00 urn:sha1:8e97b8f68d3309989115f48efc851db97f05070f Instead of going through a model #ifdef, the call to EFI_ACPI_5_1_GICC_STRUCTURE_INIT () is factorized by setting up a new set of PCDs. Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> 2020-03-25T09:36:43+00:00 Pete Batard pete@akeo.ie 2020-03-09T14:21:18+00:00 urn:sha1:dcd7e73670c444e7d436b9a2f84184ab58842f31 Silence 2 warnings from pep.asl: * "Warning 3133 - Unknown reserved name (_GPI/_GCI/_GDI)" * "Warning 3150 - Empty Resource Template", which is caused by section "Name (_CRS, ResourceTemplate () {})" Remove "Offset(0)" in Xhci.asl, which produces the warning: "Unnecessary/redundant use of Offset operator". Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>