Tianocore/edk2-platforms.git/Platform/Marvell, branch CodeCleanup

Marvell/Armada80x0Db: Fix build

2024-01-03T13:23:14+00:00

Commit ec5de71d83 ("Silicon/Marvell: Restructure package") broke Armada80x0Db build by unintentional removal of device tree component. Restore it. Signed-off-by: Marcin Wojtas

Silicon/Marvell: Restructure package

2023-11-16T17:09:52+00:00

Current Marvell package structure makes it difficult to add new silicon packages that reuse common elements without creating nested DEC files. This patch creates a new MarvellSiliconPkg folder and moves the current common elements inside it. Also gMarvellTokenSpaceGuid has been renamed to gMarvellSiliconTokenSpaceGuid to align with new package name. Signed-off-by: Narinder Dhillon Reviewed-by: Leif Lindholm

Marvell/SolidRun: Rework Readme.md files

2022-04-20T08:27:45+00:00

This patch reworks Readme.md files of Marvell and SolidRun platforms as follows: * Add supported features list. * Leave minmal EDK2 build command. * Add 'NOTE' box about INCLUDE_TFTP_COMMAND build flag. * Move full firmware image build/burn howtos to external wiki pages. * Add links and update paragraphs. Signed-off-by: Marcin Wojtas Reviewed-by: Sunny Wang

Marvell/Cn913xDbA: Add Readme.md

2021-09-21T10:04:34+00:00

Add the complete build instruction for CN913x Development Board. Signed-off-by: Marcin Wojtas

Marvell: Armada7k8k/OcteonTX: Enable additional board configuration

2021-08-02T03:30:47+00:00

Introduce new board description library extension that allows to execute custom initialization sequence. Add stubs for all existing platforms. Signed-off-by: Marcin Wojtas

Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support

2021-08-02T03:30:47+00:00

In order to support more than one PCIE port, PciHostBridgeLib must generate appropriate device paths according to the board description and assign correct segment numbers instead of a hard-coded 0. Additionally, PciSegmentLib has to operate on a proper config spaces base address (depending on the segment number). Add the library constructor routine and obtain the necessary data from the Marvell board description protocol. Remove unused PCIE-related PCD's. Signed-off-by: Marcin Wojtas

Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces

2021-08-02T03:30:47+00:00

Until now the virtual memory map for the single PCIE configuration space was hardcoded via PCDs and assumed adjacency to the SoC MMIO region (0xf0000000 - 4GB). Remove this limitation by splitting the regions and allowing to obtain the PCIE configuration space settings from ArmadaBoardDescLib. It is a preparation patch for adding support for multiple PCIE controllers. Signed-off-by: Marcin Wojtas

Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table

2021-08-01T17:12:13+00:00

The DBG2 table is mandatory as per SBBR v1.2 specification. Introduce it via CP0_UART0 interface. Note: in order to use it, DPR58 and DPR59 must be switched to positions 2-3. Signed-off-by: Marcin Wojtas

Marvell/Cn913xDb: Update AP807 MMC settings

2021-05-10T16:06:24+00:00

This patch enables switching to 1.8V power supply on the VCCQ rail of the AP807 MMC interface, which allows to operate at HS400 when booting with ACPI. Since there are issues with this mode in EDK2 Xenon SD/MMC driver apply a workaround, that limits the mode to HS200 by forcing bus width to 4. Signed-off-by: Marcin Wojtas Acked-by: Ard Biesheuvel

Marvell/Armada70x0Db: Update CP0 MMC settings

2021-05-10T16:06:19+00:00

This patch enables switching to 1.8V power supply on the VCCQ rail of the CP0 MMC interface, which allows to operate at HS200 in EDK2 and when booting with ACPI. Signed-off-by: Marcin Wojtas Acked-by: Ard Biesheuvel