<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2-platforms.git/Platform/Intel/SimicsOpenBoardPkg, branch CodeCleanup</title>
<subtitle>EDK II sample platform branches and tags (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup'/>
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<updated>2024-07-07T07:41:18+00:00</updated>
<entry>
<title>Platform/Intel: Set PcdAcpiBaseAddress for PEI MM Communication</title>
<updated>2024-07-07T07:41:18+00:00</updated>
<author>
<name>Jiaxin Wu</name>
<email>jiaxin.wu@intel.com</email>
</author>
<published>2024-06-22T06:06:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=ad553efc01125cad4ebdbe694b82cf6a59ce6a03'/>
<id>urn:sha1:ad553efc01125cad4ebdbe694b82cf6a59ce6a03</id>
<content type='text'>
Set PcdAcpiBaseAddress to 0x400 for PEI MM communication.

Signed-off-by: Wei6 Xu &lt;wei6.xu@intel.com&gt;
Co-authored-by: Jiaxin Wu &lt;jiaxin.wu@intel.com&gt;
</content>
</entry>
<entry>
<title>Platform/Intel: Install an SMM Control PPI</title>
<updated>2024-07-07T07:41:18+00:00</updated>
<author>
<name>Jiaxin Wu</name>
<email>jiaxin.wu@intel.com</email>
</author>
<published>2024-07-05T04:41:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=1fe5d09d5d03571a071222bc7a9433743533d21c'/>
<id>urn:sha1:1fe5d09d5d03571a071222bc7a9433743533d21c</id>
<content type='text'>
Install an instance of EFI_PEI_MM_CONTROL_PPI.
This PPI provides a standard way for other modules to
trigger software SMIs.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Co-authored-by: Jiaxin Wu &lt;jiaxin.wu@intel.com&gt;
</content>
</entry>
<entry>
<title>Platform/Intel: Consume SmmRelocationInit interface</title>
<updated>2024-07-05T14:28:32+00:00</updated>
<author>
<name>Jiaxin Wu</name>
<email>jiaxin.wu@intel.com</email>
</author>
<published>2024-07-05T03:42:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=12f68d29abdc9d703f67bd743fdec23ebb1e966e'/>
<id>urn:sha1:12f68d29abdc9d703f67bd743fdec23ebb1e966e</id>
<content type='text'>
Do the smm relocation during platform init.

Signed-off-by: Jiaxin Wu &lt;jiaxin.wu@intel.com&gt;
</content>
</entry>
<entry>
<title>Platform/Intel: Enable the PcdSmrrEnable</title>
<updated>2024-06-28T05:30:54+00:00</updated>
<author>
<name>Jiaxin Wu</name>
<email>jiaxin.wu@intel.com</email>
</author>
<published>2024-06-21T12:58:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=3b02f394187d2fafcd3c6608d0b9dba0fbcc8cdb'/>
<id>urn:sha1:3b02f394187d2fafcd3c6608d0b9dba0fbcc8cdb</id>
<content type='text'>
This patch is to enable the PcdSmrrEnable since the simics
report it has the capability to enable the smrr.

Signed-off-by: Jiaxin Wu &lt;jiaxin.wu@intel.com&gt;
</content>
</entry>
<entry>
<title>Platform/Intel: Add AmdSvsmLib to required DSC files</title>
<updated>2024-04-17T18:35:04+00:00</updated>
<author>
<name>Tom Lendacky</name>
<email>thomas.lendacky@amd.com</email>
</author>
<published>2024-04-15T15:01:23+00:00</published>
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<id>urn:sha1:0a3470d6d518d5a37cad6f15aa7d1bd4045dd5fb</id>
<content type='text'>
Any DSC file that uses the UefiCpuPkg MpInitLib library now requires the
AmdSvsmLib library. Update the DSC files to include the AmdSvsmLib NULL
library implementation.

Cc: Leif Lindholm &lt;quic_llindhol@quicinc.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Chasel Chiu &lt;chasel.chiu@intel.com&gt;
Cc: Kelly Steele &lt;kelly.steele@intel.com&gt;
Cc: Zailiang Sun &lt;zailiang.sun@intel.com&gt;
Signed-off-by: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
</content>
</entry>
<entry>
<title>SimicsOpenBoardPkg: auto-gen &amp; fix SEC ProcessLibraryConstructorList() decl</title>
<updated>2024-03-08T08:44:35+00:00</updated>
<author>
<name>Laszlo Ersek</name>
<email>lersek@redhat.com</email>
</author>
<published>2024-03-05T12:01:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=3b8a9a611cd64ab8063cdebff4fc23fdcd3ede5e'/>
<id>urn:sha1:3b8a9a611cd64ab8063cdebff4fc23fdcd3ede5e</id>
<content type='text'>
&lt;Library/PeimEntryPoint.h&gt; declares a bogus
ProcessLibraryConstructorList() for SimicsOpenBoardPkg's SEC module. Rely
on AutoGen for (properly) declaring ProcessLibraryConstructorList().
Update the call.

Build-tested with:

- appending the following directories to PACKAGES_PATH:

  Drivers
  Features/Intel
  Features/Intel/Debugging
  Features/Intel/Network
  Features/Intel/OutOfBandManagement
  Features/Intel/PowerManagement
  Features/Intel/SystemInformation
  Features/Intel/UserInterface
  Platform/Intel
  Silicon/Intel

- commenting out "SimicsIch10BinPkg/UndiBinary/UndiDxe.inf" in
  "Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc" and
  "Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf"

- running the command

  build -a IA32 -a X64 -b DEBUG \
    -m Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf \
    -p Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc \
    -t GCC5

Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Sai Chaganty &lt;rangasai.v.chaganty@intel.com&gt;
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=990
Signed-off-by: Laszlo Ersek &lt;lersek@redhat.com&gt;
Message-Id: &lt;20240305120126.70259-3-lersek@redhat.com&gt;
Reviewed-by: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
<entry>
<title>SimicsOpenBoardPkg: Set PcdDxeIplSwitchToLongMode to FALSE</title>
<updated>2023-07-28T03:33:46+00:00</updated>
<author>
<name>Tan, Dun</name>
<email>dun.tan@intel.com</email>
</author>
<published>2023-07-27T02:22:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=4f316893c9ed1b58a912b8546be6f87c5b61705f'/>
<id>urn:sha1:4f316893c9ed1b58a912b8546be6f87c5b61705f</id>
<content type='text'>
Set PcdDxeIplSwitchToLongMode to FALSE if the execution
mode is not IA32 PEI + X64 DXE.

Signed-off-by: Dun Tan &lt;dun.tan@intel.com&gt;
Reviewed-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Cc: Zhiguang Liu &lt;zhiguang@liu@intel.com&gt;
</content>
</entry>
<entry>
<title>SimicsOpenBoard: Use default 10ms as delay between INIT and SIPI</title>
<updated>2023-06-05T04:56:03+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2023-05-30T08:29:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=040ecd8c81a56e526d922b0ba80843dcf87a4967'/>
<id>urn:sha1:040ecd8c81a56e526d922b0ba80843dcf87a4967</id>
<content type='text'>
Today the delay is 10us but the QSP simulates the multiprocessor
by dividing time into segments and serializing processors within a
segment.
The length of the segment is configurable and Simics open board
is configured using 100us.

But the firmware configures the delay between INIT and SIPI is 10us.
That results a possible senarino that BSP sends a INIT and SIPI in one
segment (100us) while APs are still in SMM environment. The INIT is
queued but SIPI is ignored by Simics, resulting all APs being put in
wait-for-SIPI state when they receive INIT.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Reviewed-by: Zhiguang Liu &lt;zhiguang.liu@intel.com&gt;
</content>
</entry>
<entry>
<title>SimicsOpenBoardPkg: Disable DriverBindingSupport perf logging</title>
<updated>2023-05-30T08:35:38+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2023-05-24T12:27:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=02fb8459d9c48a8ed4691e9c22f2516c15073835'/>
<id>urn:sha1:02fb8459d9c48a8ed4691e9c22f2516c15073835</id>
<content type='text'>
DriverBindingSupport() is called lots of time during post.
If it's also included in the perf logging, it's very easy to use all
the FPDT table memory pre-allocated at EndOfDxe because the
driver binding connect process happens after EndOfDxe.

PcdExtFpdtBootRecordPadSize was added for holding the
perf-logging records after EndOfDxe. But the DriverBindingSupport
records are just too many. For example, SimicsOpenBoardPkg has
to set this PCD to almost 100x bigger than the default value in order
to hold all the perf-logging records.

Platform developers are usually not aware of missing some records
after EndOfDxe because those records are all about driverbinding
support/start/stop. But if we add more perf-logging inside SMM,
those SMM records will be missed in the final FPDT table because
DxeCorePerformanceLib collects those SMM records at ReadyToBoot
event. Since the FPDT cannot hold all driverbinding records, it
definitely cannot hold those SMM records as well.

So in order to hold all SMM perf loggings, either platform should
set PcdExtFpdtBootRecordPadSize to a large enough value, or
as what this patch does, to disable the driverbinding support
perf-logging.

Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Reviewed-by: Zhiguang Liu &lt;zhiguang@liu@intel.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
<entry>
<title>SimicsOpenBoardPkg: Add "dp" command in performance build</title>
<updated>2023-05-30T08:35:38+00:00</updated>
<author>
<name>Ray Ni</name>
<email>ray.ni@intel.com</email>
</author>
<published>2023-05-24T12:16:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=ddd94333f5e5e843ca1459ce25ad897da8142909'/>
<id>urn:sha1:ddd94333f5e5e843ca1459ce25ad897da8142909</id>
<content type='text'>
Signed-off-by: Ray Ni &lt;ray.ni@intel.com&gt;
Cc: Nate DeSimone &lt;nathaniel.l.desimone@intel.com&gt;
Reviewed-by: Zhiguang Liu &lt;zhiguang@liu@intel.com&gt;
Cc: Michael D Kinney &lt;michael.d.kinney@intel.com&gt;
</content>
</entry>
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