EDK II sample platform branches and tags (mirror) https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup 2024-06-24T10:19:23+00:00 2024-06-24T10:19:23+00:00 Leif Lindholm quic_llindhol@quicinc.com 2024-06-20T11:15:44+00:00 urn:sha1:d9bcbf86b03f4c96cd63a97f43b985fcaef1d12d Some Arm ltd. platforms explicitly set PcdArmArchTimerFreqInHz, however the intended effect of that is not possible from AArch64 EL2/1, and has never been performed unless built for ARM. The Pcd is now being deleted, so drop the setting. This has however affected timer timout calculations, so could lead to a change in platform behaviour. Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-21T11:31:20+00:00 Leif Lindholm quic_llindhol@quicinc.com 2024-06-20T10:11:20+00:00 urn:sha1:b29e69a688d6154a84df725cee38273553062160 PcdArmArchTimerFreqInHz is about to be removed, as it is now obsolete. Some platforms already explicitly set it to 0, which is the default. And some modules reference it in their .inf without actually ever using it. Drop these redundant uses first. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Chuong Tran <chuong@os.amperecomputing.com> Cc: Graeme Gregory <graeme@xora.org.uk> Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Cc: Nhi Pham <nhi@os.amperecomputing.com> Cc: Rebecca Cran <rebecca@os.amperecomputing.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Wenyi Xie <xiewenyi2@huawei.com> Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com> 2024-06-21T11:28:46+00:00 Leif Lindholm quic_llindhol@quicinc.com 2024-06-20T10:05:18+00:00 urn:sha1:901d6e59b9a65ccc434ce67575564b59c201164f A patch adding a mapping for ImagePropertiesRecordLib introduced a bunch of LF line endings in otherwise CRLF files, so clean that up. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Chuong Tran <chuong@os.amperecomputing.com> Cc: Graeme Gregory <graeme@xora.org.uk> Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Cc: Marcin Wojtas <marcin.s.wojtas@gmail.com> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Cc: Narinder Dhillon <ndhillon@marvell.com> Cc: Nhi Pham <nhi@os.amperecomputing.com> Cc: Rebecca Cran <rebecca@os.amperecomputing.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> 2024-06-06T14:56:28+00:00 Prabin CA prabin.ca@arm.com 2024-04-03T17:33:34+00:00 urn:sha1:8f05785753aad75e11494f6737833503e28cd45d Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a 16 core platform with Poseidon CPU. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-06T14:56:28+00:00 Pranav Madhu pranav.madhu@arm.com 2024-04-03T17:33:33+00:00 urn:sha1:5ff32472f43586ac6d78b65465cb6d29b1bd5487 The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level cache. Extend the SMBIOS support for RD-V2 platform with this configuration and reuse rest of the RD-N2 SMBIOS configuration for the RD-V2 platform. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-06T14:56:28+00:00 Pranav Madhu pranav.madhu@arm.com 2024-04-03T17:33:32+00:00 urn:sha1:024449b9fa17364e43cc206e482a765f4f9a99d9 Add RD-V2 platform identification values including the part number and configuration number. This information will be used in populating the SMBIOS tables. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-06T14:56:28+00:00 Prabin CA prabin.ca@arm.com 2024-04-03T17:33:31+00:00 urn:sha1:0ed4007dfec69589f5ea3542d0dc40ce044e3099 The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU. Use the size specified by this PCD in the PPTT table of the RD-N2 platform. The size of the CPU's L2 cache can be configured at build time using the --pcd command line option of the build command. e.g. To set the L2CacheSize to 2MB specify the pcd option as: $ build ... -p <DSC file> --pcd PcdL2CacheSize=0x200000 This allows changing the value of the L2 cache size depending the variant of the RD-N2 platform being build. RD-V2 platform is an example of such a variant. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-06T14:56:28+00:00 Prabin CA prabin.ca@arm.com 2024-04-03T17:33:30+00:00 urn:sha1:215928f5f12aa910175175217f128697836b5381 A new PCD named PcdL2CacheSize is introduced to specify the size of the CPU's L2 cache. This PCD can be used in PPTT tables for a reference design platform. The default value of this PCD is set to 1MB but can be changed depending on the variant of the reference design platform. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-05-29T15:45:58+00:00 sahil sahil@arm.com 2024-05-29T08:55:17+00:00 urn:sha1:35bca3ca71c004b7f3d93c6f33724796c6b1bf0b This driver enables Fault Tolerant Write protocol, which provides fault tolerant write capability for block devices. Signed-off-by: sahil <sahil@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-05-29T15:45:57+00:00 sahil sahil@arm.com 2024-05-29T08:55:16+00:00 urn:sha1:9498e8ab697ac0448e3462b0fcd0eab1f85962d8 Enable persistent storage on QSPI flash device. Signed-off-by: sahil <sahil@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>