<feed xmlns='http://www.w3.org/2005/Atom'>
<title>Tianocore/edk2-platforms.git/Platform/ARM/VExpressPkg/ConfigurationManager, branch CodeCleanup</title>
<subtitle>EDK II sample platform branches and tags (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup</id>
<link rel='self' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/'/>
<updated>2023-10-30T11:18:42+00:00</updated>
<entry>
<title>Platform/ARM: FVP: Add ETE device if supported by FVP</title>
<updated>2023-10-30T11:18:42+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2023-09-22T14:41:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=1ae7cffab740bb69b48d8f74f7fb64bb29677fc0'/>
<id>urn:sha1:1ae7cffab740bb69b48d8f74f7fb64bb29677fc0</id>
<content type='text'>
When ETE is enabled in the FVP model the firmware can check
the debug feature register ID_AA64DFR0_EL1.TraceVer field
to identify the presence of FEAT_ETE and add an ETE device
to the CPU node in the AML CPU hierarchy. This enables the
Operating System driver to probe and enable ETE support.

 Note: To enable ETE support in the FVP REvC model
    1. Build TF-A with the CTX_INCLUDE_AARCH32_REGS=0
       build flag set, otherwise this results in an
       exception when booting TF-A
    2. Set the model parameters to enable TRBE as this
       is required for ETE
        -C cluster0.has_trbe=1 -C cluster1.has_trbe=1
    3. Set the ETE plugin for the model
       --plugin &lt;PLUGIN_PATH&gt;\libete-plugin.[so|dll]

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: FVP: Specify TRBE interrupt in MADT GICC</title>
<updated>2023-10-30T11:18:42+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2023-09-22T14:41:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=4a52974bc6045fecaafa53732d86710358b0ea34'/>
<id>urn:sha1:4a52974bc6045fecaafa53732d86710358b0ea34</id>
<content type='text'>
When TRBE is enabled the FVP model uses the PPI 15
(i.e. INT ID 31) as the TRBE interrupt.
Ref: https://www.kernel.org/doc/Documentation/
devicetree/bindings/arm/arm,trace-buffer-extension.yaml

Therefore, check the debug feature register
ID_AA64DFR0_EL1.TraceBuffer field to see if TRBE is
enabled and configure the TRBE interrupt in the GICC
structure in the MADT ACPI table.

Note: To enable TRBE support in the FVP REvC model
1. Build TF-A with the CTX_INCLUDE_AARCH32_REGS=0
   build flag set, otherwise this results in an
   exception when booting TF-A.
2. Set the model parameters to enable TRBE
    -C cluster0.has_trbe=1 -C cluster1.has_trbe=1

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Add dynamic CPU node generation for FVP</title>
<updated>2023-10-30T11:18:42+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2023-09-22T14:41:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=ae22ad22c8438f3f53ee6338f696b5ce1998fe29'/>
<id>urn:sha1:ae22ad22c8438f3f53ee6338f696b5ce1998fe29</id>
<content type='text'>
Add support to dynamically generate the CPU nodes in SSDT.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Bump Dsdt/Ssdt ACPI table revision</title>
<updated>2022-11-01T12:06:02+00:00</updated>
<author>
<name>Pierre Gondois</name>
<email>pierre.gondois@arm.com</email>
</author>
<published>2022-09-08T13:34:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=d13436b384fc3e39e6e633b097daafd2db43bee2'/>
<id>urn:sha1:d13436b384fc3e39e6e633b097daafd2db43bee2</id>
<content type='text'>
From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block):
  Note: For compatibility with ACPI versions before
  ACPI 2.0, the bit width of Integer objects is
  dependent on the ComplianceRevision of the DSDT.
  If the ComplianceRevision is less than 2, all
  integers are restricted to 32 bits. Otherwise,
  full 64-bit integers are used. The version of the DSDT
  sets the global integer width for all integers,
  including integers in SSDTs.

To be up-to-date with the latest table revision, bump the version
of all dsdt/ssdt tables that are relying on an ACPI specification
version above 2.0.

Signed-off-by: Pierre Gondois &lt;Pierre.Gondois@arm.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: FVP: Update for IORT revision macro renaming</title>
<updated>2022-07-29T18:37:52+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2022-07-14T16:55:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=5802ce2f3f77d5f7cca8238497110aee0a1462ae'/>
<id>urn:sha1:5802ce2f3f77d5f7cca8238497110aee0a1462ae</id>
<content type='text'>
The IORT Specification E.d updates the IORT table revision to 5. To
reflect this change the IORT header file has been updated to rename
the EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro which was at Rev 0 to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Therefore, update the usage of EFI_ACPI_IO_REMAPPING_TABLE_REVISION
macro in the Configuration Manager for FVP platform to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: FVP: set IORT RC address limit for FVP RevC</title>
<updated>2022-04-29T13:31:55+00:00</updated>
<author>
<name>Edward Pickup</name>
<email>edward.pickup@arm.com</email>
</author>
<published>2022-04-19T09:26:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=38855c561f906aba762cce89cb9cf936e58006bb'/>
<id>urn:sha1:38855c561f906aba762cce89cb9cf936e58006bb</id>
<content type='text'>
When booting Linux on FVP RevC, Linux reports the following error:

ACPI: IORT: [Firmware Bug]: Root complex missing memory address limit

This issue is due to the RC Address Limit not being configured in the
configuration manager for the platform.

Set the value to 64 as the RevC FVP can use the full width, fixing the
error.

Signed-off-by: Edward Pickup &lt;edward.pickup@arm.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: FVP: Fix variable usage in GetArmNameSpaceObject()</title>
<updated>2021-07-13T17:03:13+00:00</updated>
<author>
<name>Joey Gouly</name>
<email>joey.gouly@arm.com</email>
</author>
<published>2021-07-01T12:24:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=564a6a340892959aa4eac1a7bdf10d1b708f3085'/>
<id>urn:sha1:564a6a340892959aa4eac1a7bdf10d1b708f3085</id>
<content type='text'>
Building with Clang showed that `RootComplexCount` and
`DeviceIdMappingArrayCount` were unused. Use the
variables where they were intended to be used.

Signed-off-by: Joey Gouly &lt;joey.gouly@arm.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM/VExpressPkg: Remove non-ASCII characters</title>
<updated>2021-02-17T16:36:46+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2021-02-17T15:08:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=bb1f054af0cf2d657399fcacb8f83865f86e70fd'/>
<id>urn:sha1:bb1f054af0cf2d657399fcacb8f83865f86e70fd</id>
<content type='text'>
The patch at "4be8625ab1b008057ae9a500aa8978be2a02d6e2
Platform/ARM/VExpressPkg: Add support for FVP RevC model"
introduced a new file SsdtPci.asl. The file SsdtPci.asl
had a few non-ASCII characters in the code comments.
These resulted in the Trim utility generating a warning
that caused the firmware build to fail on a Linux
development PC.

Therefore, remove the non-ASCII characters as it results
in builds failures on a Linux development PC.

Note: This issue was not observed on a Windows development
PC.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Thomas Abraham &lt;thomas.abraham@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM/VExpressPkg: Add Virtio Block Device description</title>
<updated>2021-02-13T10:24:23+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2021-01-19T19:52:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=75cd400c86d69ba99f395d8bf2afb4553c06d3b1'/>
<id>urn:sha1:75cd400c86d69ba99f395d8bf2afb4553c06d3b1</id>
<content type='text'>
The FVP model implements a Virtio block device that can be accessed from
a Guest OS if it has an appropriate driver. It is targeted primarily at
Linux, which has a built-in Virtio block driver. VirtioBlockDevice allows
to use a file on the host that is specified using the models image_path
parameter, as a hard drive in the Guest OS.

Therefore, add the Virtio block device description to the DSDT.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Platform/ARM/VExpressPkg: Add SMC91x device description</title>
<updated>2021-02-13T10:24:20+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2021-01-19T19:39:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=a2948e712748c42e3f0164cdfedd978ff27f7b0e'/>
<id>urn:sha1:a2948e712748c42e3f0164cdfedd978ff27f7b0e</id>
<content type='text'>
The FVP model implements a SMSC 91C111 ethernet controller that
can be configured for network access.

Therefore, add description for a SMSC 91C111 device in the DSDT.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
</feed>
