Tianocore/edk2-platforms.git/Platform/ARM/SgiPkg, branch CodeCleanupEDK II sample platform branches and tags (mirror)https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup2024-06-24T10:19:23+00:00Platform/ARM: drop use of PcdArmArchTimerFreqInHz2024-06-24T10:19:23+00:00Leif Lindholmquic_llindhol@quicinc.com2024-06-20T11:15:44+00:00urn:sha1:d9bcbf86b03f4c96cd63a97f43b985fcaef1d12d
Some Arm ltd. platforms explicitly set PcdArmArchTimerFreqInHz, however
the intended effect of that is not possible from AArch64 EL2/1, and has
never been performed unless built for ARM.
The Pcd is now being deleted, so drop the setting.
This has however affected timer timout calculations, so could lead to a
change in platform behaviour.
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Extend SMBIOS support for RD-Fremont2024-06-06T14:56:28+00:00Prabin CAprabin.ca@arm.com2024-04-03T17:33:34+00:00urn:sha1:8f05785753aad75e11494f6737833503e28cd45d
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Extend SMBIOS support for RD-V2 platform2024-06-06T14:56:28+00:00Pranav Madhupranav.madhu@arm.com2024-04-03T17:33:33+00:00urn:sha1:5ff32472f43586ac6d78b65465cb6d29b1bd5487
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Define RD-V2 platform id values2024-06-06T14:56:28+00:00Pranav Madhupranav.madhu@arm.com2024-04-03T17:33:32+00:00urn:sha1:024449b9fa17364e43cc206e482a765f4f9a99d9
Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Use PCD value for L2 cache size in PPTT table2024-06-06T14:56:28+00:00Prabin CAprabin.ca@arm.com2024-04-03T17:33:31+00:00urn:sha1:0ed4007dfec69589f5ea3542d0dc40ce044e3099
The PcdL2CacheSize PCD specifies the size of L2 cache of the
CPU. Use the size specified by this PCD in the PPTT table of
the RD-N2 platform.
The size of the CPU's L2 cache can be configured at build time
using the --pcd command line option of the build command.
e.g. To set the L2CacheSize to 2MB specify the pcd option as:
$ build ... -p <DSC file> --pcd PcdL2CacheSize=0x200000
This allows changing the value of the L2 cache size depending
the variant of the RD-N2 platform being build. RD-V2 platform
is an example of such a variant.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Add a new PCD for L2 cache size2024-06-06T14:56:28+00:00Prabin CAprabin.ca@arm.com2024-04-03T17:33:30+00:00urn:sha1:215928f5f12aa910175175217f128697836b5381
A new PCD named PcdL2CacheSize is introduced to specify the size of the
CPU's L2 cache. This PCD can be used in PPTT tables for a reference
design platform. The default value of this PCD is set to 1MB but can be
changed depending on the variant of the reference design platform.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/ARM: Add optional provision to fetch and print NOR Flash info2024-05-29T15:45:55+00:00sahilsahil@arm.com2024-05-29T08:55:12+00:00urn:sha1:ed8969bc7bbff30c3b9d725789cbba997721e25e
This patch adds an optional functionality in NorFlashDxe to fetch and
print NOR Flash information from NorFlashInfoLib using its JEDEC ID.
NOR Flash libraries will implement a function "NorFlashReadID" which
will fetch and return JEDEC ID. This JEDEC ID can be then printed
along with the NOR Flash info by NorFlashInfoLib. If this functionality
is not needed then the function can just return EFI_UNSUPPORTED.
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/ARM/NorFlashDxe: Switch from NorFlash.c to NorFlashDeviceLib2024-05-29T15:45:54+00:00sahilsahil@arm.com2024-05-29T08:55:09+00:00urn:sha1:44c4c207aeaa9f315ce7cf14fbd0cdbacd2dfdc4
NorFlashDeviceLib can be used to provide implementations of different
NOR Flash to NorFlashDxe, i.e. NorFlashDxe links with NorFlashDeviceLib
and the platforms can specify their respective NorFlashDeviceLib
instances.
This patch adds the following major changes:
1. Adds changes in NorFlashDxe to look for NorFlashDeviceLib instead of
NorFlash.c for flash specific implementation
2. Remove NorFlash.c and NorFlash.h as they are no longer required.
3. Add changes to platform description files to provide
P30NorFlashDeviceLib as NorFlashDeviceLib
Signed-off-by: sahil <sahil@arm.com>
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: levi.yun <yeoreum.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Add CPPC support for RD-Fremont platform2024-03-31T12:00:55+00:00Prabin CAprabin.ca@arm.com2024-03-11T13:14:16+00:00urn:sha1:b64443f7b8c37b90e04e08bb8dd0ce48fa602580
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set the
desired performance. In addition to this, RD-Fremont platform does not
support CPPC revision 1 and below. So update the _OSC method to let OSPM
know about this fact.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Platform/Sgi: Low Power Idle States for RD-Fremont2024-03-31T12:00:54+00:00Prabin CAprabin.ca@arm.com2024-03-11T13:14:15+00:00urn:sha1:4c3a1af527181682f511f7d942c88ed8fdcc969c
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Reviewed-by: levi.yun <yeoreurm.yun@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>