EDK II sample platform branches and tags (mirror) https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup 2024-06-06T14:56:28+00:00 2024-06-06T14:56:28+00:00 Prabin CA prabin.ca@arm.com 2024-04-03T17:33:34+00:00 urn:sha1:8f05785753aad75e11494f6737833503e28cd45d Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a 16 core platform with Poseidon CPU. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-06T14:56:28+00:00 Pranav Madhu pranav.madhu@arm.com 2024-04-03T17:33:32+00:00 urn:sha1:024449b9fa17364e43cc206e482a765f4f9a99d9 Add RD-V2 platform identification values including the part number and configuration number. This information will be used in populating the SMBIOS tables. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-03-31T11:18:46+00:00 Prabin CA prabin.ca@arm.com 2024-03-11T13:14:08+00:00 urn:sha1:2a248c313232a85ff39f3739813764e28bd4c8aa The reference design platform currently lacks the CPPC (Collaborative Processor Performance Control) performance limited register as defined by the ACPI 6.x specification. There is a typo in the macro definition where the 'fastchannel address of the performance limited register' is mentioned instead of the 'performance limited register address'. Correcting this typo. However, it's important to retain the reference to the performance limited register in the macro for future use, as it will prove useful once functionalities such as power metering devices are enabled. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreurm.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2023-04-26T15:53:37+00:00 Vivek Gautam vivek.gautam@arm.com 2023-03-24T11:03:01+00:00 urn:sha1:d5176109e16a6d3291c99e5f30f6acd996e188bd Arm reference design platforms have multiple IO virtualization blocks that allow connecting PCIe root bus or non-PCIe SoC peripherals to the system. Each of these IO virtualization blocks consists of an instance of SMMUv3, a GIC-ITS and a NCI (network chip interconnect) to support traffic flow and address mapping, as required. The SoC expansion blocks that connect to the IO virtualization block include devices such as UARTs, DMAs and few additional memory nodes. For platforms having SoC expansion block connected to the IO virtualization block add a SSDT table to describe devices included in the SoC expansion block. Preprocessor macros are also added in this change to allow scalability for platforms that implement multiple instances of these SoC expansion blocks. Signed-off-by: Vivek Gautam <vivek.gautam@arm.com> Reviewed-by: Pierre Gondois: <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2022-06-27T06:33:24+00:00 Vijayenthiran Subramaniam vijayenthiran.subramaniam@arm.com 2021-08-05T04:41:22+00:00 urn:sha1:5d44ddb37a6d6a5d266d007f6915939e16d61eff The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform but with reduced core count, that is, each instance of the RD-N2 chip has four cores. This platform shares the same product and config ID as the RD-N2 platform. As a preparatory step towards adding support for RD-N2-Cfg2 Platfrom, add the Product ID lookup values for GetProductID API. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> 2022-06-27T06:33:23+00:00 Vijayenthiran Subramaniam vijayenthiran.subramaniam@arm.com 2022-01-27T17:53:59+00:00 urn:sha1:e573be8e5110fa1570338f9308bd85a6aeac7751 Add a new PCD to define the maximum number of address bits used for addresses within a chip. The value of this PCD can be used to derive the maximum addressable memory region for each chip and to calculate the address space offset of a remote chip on multi-chip platform. In preparation of adding a multi-chip variant of the RD-N2 platform, use this new PCD to allow maximum address space of 64TB per chip for all RD-N2 platform variants. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> 2022-06-27T06:06:35+00:00 Pranav Madhu pranav.madhu@arm.com 2022-01-03T17:35:23+00:00 urn:sha1:e6f8685f71d5e12f1d4fd5472cec87b3f0cf123a Update the common ACPI tables used by all the Neoverse Reference Design platforms to ACPI version v6.4. Significant changes introduced are update API/macro definitions to incorporate with the extra fields introduced in ACPI 6.4, such as SPE overflow interrupt number field to GICC structure of MADT table and adding cache ID field to the cache structure of PPTT table. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> 2022-05-03T09:11:21+00:00 Pranav Madhu pranav.madhu@arm.com 2022-04-18T08:14:03+00:00 urn:sha1:df5e094ef347d12f48c306268c674df40a1357da Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the Neoverse reference design platforms is the memory side cache and so it is removed from PPTT table. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> 2021-07-05T14:25:44+00:00 Pranav Madhu pranav.madhu@arm.com 2021-06-11T10:34:20+00:00 urn:sha1:5bf71dc8978166ff6993b6da79bcb136fcabc1ec Define and use the global macro LPI_EN and CPPC_EN to enable low power idle and CPPC support for reference design platforms. Update platform wide _OSC control method to enable/disable low power idle and CPPC support based on pcd PcdOscLpiEnable and PcdOscCppcEnable. The pcds are controlled by the global macros LPI_EN and CPPC_EN. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-06-01T15:22:51+00:00 Pranav Madhu pranav.madhu@arm.com 2021-05-25T10:58:00+00:00 urn:sha1:d447392ad5ca526601afe90e71266855f6545adb Add the RD-N2-Cfg1 platform identification values including the part number and configuration number. This information will be used in populating the SMBIOS tables. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>