EDK II sample platform branches and tags (mirror) https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup 2024-06-06T14:56:28+00:00 2024-06-06T14:56:28+00:00 Prabin CA prabin.ca@arm.com 2024-04-03T17:33:34+00:00 urn:sha1:8f05785753aad75e11494f6737833503e28cd45d Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a 16 core platform with Poseidon CPU. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. The platform also includes system level cache of 32MB and 8GB of RAM. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-06-06T14:56:28+00:00 Pranav Madhu pranav.madhu@arm.com 2024-04-03T17:33:33+00:00 urn:sha1:5ff32472f43586ac6d78b65465cb6d29b1bd5487 The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level cache. Extend the SMBIOS support for RD-V2 platform with this configuration and reuse rest of the RD-N2 SMBIOS configuration for the RD-V2 platform. Signed-off-by: Prabin CA <prabin.ca@arm.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2023-04-26T15:57:06+00:00 Shriram K shriram.k@arm.com 2023-03-24T11:03:02+00:00 urn:sha1:91ef09df30ebeb9b8c987b83ef9ec474b52bb9ee The IO virtualization block on reference design platforms allow connecting SoC expansion devices such as PL011 UART. On platforms that support this, initialize the UART controller connected to the IO virtualization block. Signed-off-by: Shriram K <shriram.k@arm.com> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com> Reviewed-by: Pierre Gondois: <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2022-06-27T06:33:28+00:00 Pranav Madhu pranav.madhu@arm.com 2021-09-14T13:27:09+00:00 urn:sha1:f653a22385f502a021dced5fe174ab03b7c2be29 Extend the SMBIOS support for RD-N2-Cfg2 platform which is a quad-chip variant of the RD-N2 platform. Most the SMBIOS information is shared with the RD-N2 platform except for the number of the CPUs supported on the RD-N2-Cfg2 platform. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> 2022-01-24T12:44:07+00:00 Pierre Gondois Pierre.Gondois@arm.com 2021-10-26T12:56:47+00:00 urn:sha1:2d310c3350f49dee89d365f4b7feb994ef6b2ed8 This patch fixes the following Ecc reported error: File has invalid Non-ACSII char. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Chris Jones <christopher.jones@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-06-01T15:22:57+00:00 Pranav Madhu pranav.madhu@arm.com 2021-05-25T10:58:01+00:00 urn:sha1:f7c08b9bae565c911bf2eb92a0c66dc496c28eec Extend the SMBIOS support for RD-N2-Cfg1 platform. RD-N2-Cfg1 platform is a derivative of the RD-N2 platform and so most of the table values for RD-N2 platform is reused. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-06-01T14:21:52+00:00 Pranav Madhu pranav.madhu@arm.com 2021-05-24T14:28:16+00:00 urn:sha1:8cdd4cb7c71ebc1e89c97f61e4d33ec99c3fe725 Add the SMBIOS type 32 table (System Boot Information) that includes information about the System Boot Status. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-06-01T14:21:46+00:00 Pranav Madhu pranav.madhu@arm.com 2021-05-24T14:28:15+00:00 urn:sha1:91b1983ba7312cbf67dc5747af5c2fc476dfec1d Add the SMBIOS type 19 table (Memory Array Mapped Addr) that includes information about the address mapping for a Physical Memory Array. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-06-01T14:21:40+00:00 Pranav Madhu pranav.madhu@arm.com 2021-05-24T14:28:14+00:00 urn:sha1:0697444b2cf7e1580befdc75086fa922f668f676 Add the SMBIOS type 17 table (Memory Device) that includes the specification of each installed memory device such as size of each device, bank locator, memory device type, and other related information. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-06-01T14:21:34+00:00 Pranav Madhu pranav.madhu@arm.com 2021-05-24T14:28:13+00:00 urn:sha1:9d935e0916b7cba59afb444835ab0df15bb22b83 Add the SMBIOS type 16 table (Physical Memory Array) describes a collection of memory devices that operate together to form a memory address. It includes information about number of devices, total memory installed, error correction mechanism used and other related information. Signed-off-by: Pranav Madhu <pranav.madhu@arm.com> Reviewed-by: Thomas Abraham <thomas.abraham@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>