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<title>Tianocore/edk2-platforms.git/Platform/ARM/Morello, branch CodeCleanup</title>
<subtitle>EDK II sample platform branches and tags (mirror)</subtitle>
<id>https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup</id>
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<updated>2024-06-24T10:19:23+00:00</updated>
<entry>
<title>Platform/ARM: drop use of PcdArmArchTimerFreqInHz</title>
<updated>2024-06-24T10:19:23+00:00</updated>
<author>
<name>Leif Lindholm</name>
<email>quic_llindhol@quicinc.com</email>
</author>
<published>2024-06-20T11:15:44+00:00</published>
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<id>urn:sha1:d9bcbf86b03f4c96cd63a97f43b985fcaef1d12d</id>
<content type='text'>
Some Arm ltd. platforms explicitly set PcdArmArchTimerFreqInHz, however
the intended effect of that is not possible from AArch64 EL2/1, and has
never been performed unless built for ARM.

The Pcd is now being deleted, so drop the setting.

This has however affected timer timout calculations, so could lead to a
change in platform behaviour.

Cc: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Cc: Thomas Abraham &lt;thomas.abraham@arm.com&gt;
Signed-off-by: Leif Lindholm &lt;quic_llindhol@quicinc.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/SbsaQemu: fix .dsc line endings</title>
<updated>2024-06-21T11:28:46+00:00</updated>
<author>
<name>Leif Lindholm</name>
<email>quic_llindhol@quicinc.com</email>
</author>
<published>2024-06-20T10:05:18+00:00</published>
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<id>urn:sha1:901d6e59b9a65ccc434ce67575564b59c201164f</id>
<content type='text'>
A patch adding a mapping for ImagePropertiesRecordLib introduced a bunch of
LF line endings in otherwise CRLF files, so clean that up.

Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Chuong Tran &lt;chuong@os.amperecomputing.com&gt;
Cc: Graeme Gregory &lt;graeme@xora.org.uk&gt;
Cc: Marcin Juszkiewicz &lt;marcin.juszkiewicz@linaro.org&gt;
Cc: Marcin Wojtas &lt;marcin.s.wojtas@gmail.com&gt;
Cc: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Cc: Narinder Dhillon &lt;ndhillon@marvell.com&gt;
Cc: Nhi Pham &lt;nhi@os.amperecomputing.com&gt;
Cc: Rebecca Cran &lt;rebecca@os.amperecomputing.com&gt;
Cc: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Cc: Thomas Abraham &lt;thomas.abraham@arm.com&gt;
Signed-off-by: Leif Lindholm &lt;quic_llindhol@quicinc.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Reviewed-by: Marcin Juszkiewicz &lt;marcin.juszkiewicz@linaro.org&gt;
</content>
</entry>
<entry>
<title>Platform/ARM/Morello: Add ImagePropertiesRecordLib Instance</title>
<updated>2023-12-01T08:02:04+00:00</updated>
<author>
<name>Taylor Beebe</name>
<email>taylor.d.beebe@gmail.com</email>
</author>
<published>2023-12-01T00:34:24+00:00</published>
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<id>urn:sha1:b5ad5743ee0d1371306959896273066191d1a90b</id>
<content type='text'>
ImagePropertiesRecordLib is used by DxeMain and PiSmmCore, so it
needs to be added to most platforms.

Signed-off-by: Taylor Beebe &lt;taylor.d.beebe@gmail.com&gt;
Cc: Ard Biesheuvel &lt;ardb+tianocore@kernel.org&gt;
Cc: Thomas Abraham &lt;thomas.abraham@arm.com&gt;
Cc: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Update Morello and N1Sdp to use PrePeiCoreUniCore</title>
<updated>2022-12-13T15:00:28+00:00</updated>
<author>
<name>Rebecca Cran</name>
<email>rebecca@quicinc.com</email>
</author>
<published>2022-10-25T20:56:42+00:00</published>
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<id>urn:sha1:425cce5415176998da117e6433382ee771557900</id>
<content type='text'>
Modern platforms that use TF-A should use PrePeiCoreUniCore, since
any secondary cores will be put in the TF-A holding pen and won't
reach EDK2.

Update the Morello and N1Sdp files to use PrePeiCoreUniCore instead of
PrePeiCoreMPCore.

Signed-off-by: Rebecca Cran &lt;rebecca@quicinc.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Bump Dsdt/Ssdt ACPI table revision</title>
<updated>2022-11-01T12:06:02+00:00</updated>
<author>
<name>Pierre Gondois</name>
<email>pierre.gondois@arm.com</email>
</author>
<published>2022-09-08T13:34:16+00:00</published>
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<id>urn:sha1:d13436b384fc3e39e6e633b097daafd2db43bee2</id>
<content type='text'>
From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block):
  Note: For compatibility with ACPI versions before
  ACPI 2.0, the bit width of Integer objects is
  dependent on the ComplianceRevision of the DSDT.
  If the ComplianceRevision is less than 2, all
  integers are restricted to 32 bits. Otherwise,
  full 64-bit integers are used. The version of the DSDT
  sets the global integer width for all integers,
  including integers in SSDTs.

To be up-to-date with the latest table revision, bump the version
of all dsdt/ssdt tables that are relying on an ACPI specification
version above 2.0.

Signed-off-by: Pierre Gondois &lt;Pierre.Gondois@arm.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Morello: Update for IORT revision macro renaming</title>
<updated>2022-07-29T18:37:59+00:00</updated>
<author>
<name>Sami Mujawar</name>
<email>sami.mujawar@arm.com</email>
</author>
<published>2022-07-14T16:55:21+00:00</published>
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<id>urn:sha1:987043cfc82bbf67495864208fdab4d9487a18a6</id>
<content type='text'>
The IORT Specification E.d updates the IORT table revision to 5. To
reflect this change the IORT header file has been updated to rename
the EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro which was at Rev 0 to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Therefore, update the usage of EFI_ACPI_IO_REMAPPING_TABLE_REVISION
macro in the Configuration Manager for Morello FVP to
EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00.

Signed-off-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
Reviewed-by: Pierre Gondois &lt;pierre.gondois@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Add BootDiscoveryPolicy</title>
<updated>2022-01-28T14:06:15+00:00</updated>
<author>
<name>Pierre Gondois</name>
<email>Pierre.Gondois@arm.com</email>
</author>
<published>2022-01-28T13:17:03+00:00</published>
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<id>urn:sha1:1bbfeb030a553f32a78a136662afad515a895aeb</id>
<content type='text'>
This commit adds code which check BootDiscoveryPolicy variable and
calls Boot Policy Manager Protocol to connect device specified by
the variable. To enable that mechanism for platform
EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
added to DSC file.
For the edk2 repository, commit cae735f61328 ("ArmPkg: Enable boot
discovery policy for ARM package.") adds a mechanism to check for
the boot discovery policy. When the following are available:
- gEfiBootManagerPolicyProtocolGuid protocol
- BOOT_DISCOVERY_POLICY_VAR variable
this allows to choose whether devices need to be connected during
boot.

During boot on ARM platforms, all devices are connected if there
are no valid boot options. If the UEFI shell is added as a valid
boot option, some devices won't be connected. The BootDiscoveryPolicy
will allow to manually configure this.

For all ARM platforms, add:
- BootManagerPolicyDxe module to Bds phase
- BootDiscoveryPolicyUiLib to UiApp module
- PcdBootDiscoveryPolicy Pcd

Signed-off-by: Pierre Gondois &lt;Pierre.Gondois@arm.com&gt;
Reviewed-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
</content>
</entry>
<entry>
<title>Platform/ARM: Modify duplicated GUID in PciHostBridgeLib</title>
<updated>2022-01-24T12:44:06+00:00</updated>
<author>
<name>Pierre Gondois</name>
<email>Pierre.Gondois@arm.com</email>
</author>
<published>2021-10-26T08:55:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/Tianocore/edk2-platforms.git/commit/?id=d9694478a6f067d8446ccd50af00065b632e4bdc'/>
<id>urn:sha1:d9694478a6f067d8446ccd50af00065b632e4bdc</id>
<content type='text'>
The two following modules have the same GUID:
- Platform/ARM/Morello/Library/PciHostBridgeLib/
  PciHostBridgeLibFvp.inf
- Platform/ARM/SgiPkg/Library/PciHostBridgeLib/
  PciHostBridgeLib.inf

The module in the SgiPkg was created first. Update the GUID
of the module in the Morello folder.

Signed-off-by: Pierre Gondois &lt;Pierre.Gondois@arm.com&gt;
Reviewed-by: Chris Jones &lt;christopher.jones@arm.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM/Morello: Correct the private resources in PPTT</title>
<updated>2021-06-07T14:10:19+00:00</updated>
<author>
<name>Chandni Cherukuri</name>
<email>chandni.cherukuri@arm.com</email>
</author>
<published>2021-05-19T13:34:38+00:00</published>
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<id>urn:sha1:442dfd5da6475dfa844894bf88284b959b1210b8</id>
<content type='text'>
As per ACPI specification, only the head of the list needs to be
listed as a resources by a processor node, as cache node itself
contains a link to the next level of cache.

Signed-off-by: Chandni Cherukuri &lt;chandni.cherukuri@arm.com&gt;
Reviewed-by: Chris Jones &lt;christopher.jones@arm.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
<entry>
<title>Platform/ARM/Morello: Add virtio net support</title>
<updated>2021-04-19T13:16:26+00:00</updated>
<author>
<name>Chandni Cherukuri</name>
<email>chandni.cherukuri@arm.com</email>
</author>
<published>2021-04-19T05:40:43+00:00</published>
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<id>urn:sha1:8710e08f9e0889b8ce142ca51ad3f707009c64a6</id>
<content type='text'>
This patch registers a virtio net device for Morello
FVP platform.

Signed-off-by: Chandni Cherukuri &lt;chandni.cherukuri@arm.com&gt;
Reviewed-by: Sami Mujawar &lt;sami.mujawar@arm.com&gt;
</content>
</entry>
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