EDK II sample platform branches and tags (mirror) https://git.radix-linux.su/Tianocore/edk2-platforms.git/atom?h=CodeCleanup 2024-01-30T14:15:55+00:00 2024-01-30T14:15:55+00:00 Pierre Gondois pierre.gondois@arm.com 2024-01-29T12:08:25+00:00 urn:sha1:d9070fb98d5d5cd9fb861ceed7653b9a0d6c3309 The SsdtCpuTopologyGenerator can generate _CPC objects. This is done by querying the SCP for the relevant performance state information through SCMI. CM_ARM_CPC_INFO are then populated and used to generate _CPC objects in the Ssdt Cpu topology. Use the DynamicTablesScmiInfoLib and add the handling to generate _CPC information. Note that using _CPC is only possible if SCP is correctly tuned to advertise performance levels on an abstract and unified scale. A basic check is done to prevent the _CPC generation otherwise. Perf level values used for testing: - little CPUs OPPs: [181, 322, 383] * 1000 - big CPUs OPPs: [512, 833, 1024] * 1000 Also make use of the newly added PcdDevelopmentPlatformRelaxations and add a new ENABLE_CPC build parameter ('-D ENABLE_CPC') to enable CPC generation. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2024-01-30T14:06:48+00:00 Pierre Gondois pierre.gondois@arm.com 2024-01-29T12:08:24+00:00 urn:sha1:29dfaefcbb21cc0f21b7fb8237de1f6137764492 The SsdtCpuTopologyGenerator can generate _PSD objects. Add _PSD information and handling to the Configuration Manager to generate them. Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> 2024-01-30T14:06:48+00:00 Pierre Gondois pierre.gondois@arm.com 2024-01-29T12:08:23+00:00 urn:sha1:d7f0d0c78029ded6996cf81ef5d4bd613bd9914c Fix a typo. Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> 2023-09-11T11:16:38+00:00 Sami Mujawar sami.mujawar@arm.com 2023-06-07T15:25:35+00:00 urn:sha1:fc22c0e6970924ab77c1cbb7127bf71f233a995a Juno includes a system-level wakeup timer which is an implementation of the ARM Generic Timer architecture. The CNTCTL frame contains some registers that are accessible using a Non-Secure access. Juno R0 incorrectly limits these accesses to Secure access only. This issue is documented in the Juno Errata 832219: APB port security breaks SBSA compliance https://developer.arm.com/documentation/epm008857/latest This results in a crash when the OS tries to access these registers. Therefore, disable memory mapped platform timers for Juno R0. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Sudeep Holla <Sudeep.Holla@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reported-by: Sudeep Holla <Sudeep.Holla@arm.com> Tested-by: Sudeep Holla <Sudeep.Holla@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> 2022-11-01T12:06:02+00:00 Pierre Gondois pierre.gondois@arm.com 2022-09-08T13:34:16+00:00 urn:sha1:d13436b384fc3e39e6e633b097daafd2db43bee2 From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block): Note: For compatibility with ACPI versions before ACPI 2.0, the bit width of Integer objects is dependent on the ComplianceRevision of the DSDT. If the ComplianceRevision is less than 2, all integers are restricted to 32 bits. Otherwise, full 64-bit integers are used. The version of the DSDT sets the global integer width for all integers, including integers in SSDTs. To be up-to-date with the latest table revision, bump the version of all dsdt/ssdt tables that are relying on an ACPI specification version above 2.0. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2022-07-18T14:15:54+00:00 Pierre Gondois Pierre.Gondois@arm.com 2022-04-27T14:59:43+00:00 urn:sha1:31bd1678a1db92aa10a2324ea8fbf30ec16dad2c The Dynamic Tables Framework has been updated to add support for generating an ASL description of PCIe busses. This patch: - Describes the PCI address-range mapping and PCI devices legacy interrupts in the Configuration Manager of the Juno - Add the generation of a new SSDT table describing the PCIe bus - Removes the existing (and hard-coded) SSDT table describing the PCIe bus Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2022-07-18T14:15:47+00:00 Pierre Gondois Pierre.Gondois@arm.com 2022-04-27T14:59:42+00:00 urn:sha1:b5225e28cbe28d2bc18adcef1c895e665f8f0d1d The values printed in the 'DEBUG' are not printed in the right order. Re-order them. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2022-07-18T14:15:09+00:00 Pierre Gondois Pierre.Gondois@arm.com 2022-04-27T14:59:41+00:00 urn:sha1:452b71edddea0dadea2fdde6646ab330623bcdf2 The Dynamic Tables Framework has been updated to add support for generating an ASL description of a CPU topology and its _LPI states. This patch: - Describes the _LPI states in the Configuration Manager of the Juno - Add the generation of a new SSDT table describing the CPU topology and its _LPI states - Removes the CPU topology description of the DSDT table Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2022-04-01T15:47:09+00:00 Rebecca Cran rebecca@bsdio.com 2022-03-19T20:13:11+00:00 urn:sha1:5e208bdccc6aeddee98424569e90473a11186a34 Instead of using a custom Pcd for the ECAM address (gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress), use the Pcd from MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> 2021-01-25T12:54:35+00:00 Sami Mujawar sami.mujawar@arm.com 2021-01-22T13:29:34+00:00 urn:sha1:0c417ff511632e47601c581f14a433a707a1da98 Dynamic Tables Framework has been updated to add support for Dynamic AML. The SPCR and DBG generators have also been updated to dynamically generate the AML description for the Serial Ports. Therefore, the SSDT serial port description is redundant when Dynamic Tables Framework is enabled, so remove it. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>